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/Zephyr-latest/dts/bindings/interrupt-controller/
Dnuvoton,npcx-miwu-int-map.yaml4 description: NPCX-MIWU group-interrupt mapping child node
6 compatible: "nuvoton,npcx-miwu-int-map"
12 description: parent device node of miwu groups
15 description: Child node to present the mapping between MIWU group and interrupt
20 description: irq for miwu group
24 description: irq's priority for miwu group. The valid number is from 0 to 7.
28 description: group bit-mask for miwu interrupts
Dnuvoton,npcx-miwu.yaml4 description: Nuvoton, NPCX Multi-Input Wake-Up Unit (MIWU) node
6 compatible: "nuvoton,npcx-miwu"
14 description: index of miwu device
16 "#miwu-cells":
19 description: Number of items to present a MIWU input source specifier
21 miwu-cells:
Dnuvoton,npcx-miwu-wui-map.yaml4 description: NPCX-MIWU Wake-Up Unit Input (WUI) mapping child node
6 compatible: "nuvoton,npcx-miwu-wui-map"
9 description: Child node to present the mapping between input of MIWU and its source device
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-miwus-wui-map.dtsi12 /* Mapping between MIWU wui bits and source device */
14 compatible = "nuvoton,npcx-miwu-wui-map";
16 /* MIWU table 1 */
17 /* MIWU group A */
22 /* MIWU group G */
27 /* MIWU table 2 */
28 /* MIWU group F */
39 /* MIWU group G */
Dnpcx9-miwus-int-map.dtsi7 /* Common MIWU group-interrupt mapping configurations in npcx family */
10 /* Specific MIWU group-interrupt mapping configurations in npcx9 series */
12 /* Mapping between MIWU group and interrupts */
15 compatible = "nuvoton,npcx-miwu-int-map";
51 compatible = "nuvoton,npcx-miwu-int-map";
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-miwus-wui-map.dtsi12 /* Mapping between MIWU wui bits and source device */
14 compatible = "nuvoton,npcx-miwu-wui-map";
16 /* MIWU table 0 */
17 /* MIWU group H */
22 /* MIWU table 1 */
23 /* MIWU group B */
28 /* MIWU group G */
33 /* MIWU table 2 */
34 /* MIWU group E */
48 /* MIWU group F */
[all …]
Dnpcx4-miwus-int-map.dtsi7 /* Common MIWU group-interrupt mapping configurations in npcx family */
10 /* Specific MIWU group-interrupt mapping configurations in npcx4 series */
12 /* Mapping between MIWU group and interrupts */
15 compatible = "nuvoton,npcx-miwu-int-map";
51 compatible = "nuvoton,npcx-miwu-int-map";
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx7/
Dnpcx7-miwus-wui-map.dtsi12 /* Mapping between MIWU wui bits and source device */
14 compatible = "nuvoton,npcx-miwu-wui-map";
16 /* MIWU table 0 */
17 /* MIWU group A */
22 /* MIWU group A */
27 /* MIWU group G */
Dnpcx7-miwus-int-map.dtsi7 /* Common MIWU group-interrupt mapping configurations in npcx family */
10 /* Specific MIWU group-interrupt mapping configurations in npcx7 series */
12 /* Mapping between MIWU group and interrupts */
15 compatible = "nuvoton,npcx-miwu-int-map";
31 compatible = "nuvoton,npcx-miwu-int-map";
/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_miwu.h40 /* Interrupt modes supported by npcx miwu modules */
46 /* Interrupt trigger modes supported by npcx miwu modules */
53 /* NPCX miwu driver callback type */
63 * of Multi-Input Wake-Up Unit (MIWU) modules.
66 uint8_t table:2; /** A source belongs to which MIWU table. */
67 uint8_t group:3; /** A source belongs to which group of MIWU table. */
68 uint8_t bit:3; /** A source belongs to which bit of MIWU group. */
72 * Define npcx miwu driver callback handler signature for wake-up input source
80 * @brief MIWU/GPIO information structure
82 * It contains both GPIO and MIWU information which is stored in unused field
[all …]
Dsoc_dt.h246 * @param i index of npcx miwu devices
252 * @brief Get the index prop from parent MIWU device node.
256 * "nuvoton,npcx-miwu".
266 * @return implementation to initialize interrupts of MIWU groups and enable
/Zephyr-latest/drivers/interrupt_controller/
DKconfig.npcx7 bool "Nuvoton NPCX embedded controller (EC) miwu driver"
11 This option enables the Multi-Input Wake-Up Unit (MIWU) driver
19 Workaround the issue "MIWU Any Edge Trigger Condition"
Dintc_miwu.c11 * @brief Nuvoton NPCX MIWU driver
13 * The device Multi-Input Wake-Up Unit (MIWU) supports the Nuvoton embedded
17 * of NVIC. The NPCX series has three identical MIWU modules: MIWU0, MIWU1,
22 * MIWU and the other devices in different npcx series. For npcx7 series,
26 * 2. npcxn-miwus-int-map.dtsi: it presents relationship between MIWU group
63 /* MIWU module instances */
75 /* miwu controller base address */
77 /* index of miwu controller */
83 /* Callback functions list for each MIWU group */
102 /* MIWU local functions */
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-miwus-wui-map.dtsi8 /* Mapping between MIWU wui bits and source device */
10 compatible = "nuvoton,npcx-miwu-wui-map";
12 /* MIWU table 0 */
13 /* MIWU group A */
30 /* MIWU group B */
56 /* MIWU group C */
82 /* MIWU group D */
108 /* MIWU group E */
134 /* MIWU group F */
160 /* MIWU group G */
[all …]
Dnpcx-miwus-int-map.dtsi8 /* Mapping between MIWU group and interrupts */
11 compatible = "nuvoton,npcx-miwu-int-map";
27 compatible = "nuvoton,npcx-miwu-int-map";
73 compatible = "nuvoton,npcx-miwu-int-map";
Dnpcx.dtsi102 miwu0: miwu@400bb000 {
103 compatible = "nuvoton,npcx-miwu";
106 #miwu-cells = <2>;
109 miwu1: miwu@400bd000 {
110 compatible = "nuvoton,npcx-miwu";
113 #miwu-cells = <2>;
116 miwu2: miwu@400bf000 {
117 compatible = "nuvoton,npcx-miwu";
120 #miwu-cells = <2>;
Dnpcx7.dtsi9 /* NPCX7 series mapping table between MIWU wui bits and source device */
11 /* NPCX7 series mapping table between MIWU groups and interrupts */
Dnpcx9.dtsi9 /* NPCX9 series mapping table between MIWU wui bits and source device */
11 /* NPCX9 series mapping table between MIWU groups and interrupts */
Dnpcx4.dtsi9 /* npcx4 series mapping table between MIWU wui bits and source device */
11 /* npcx4 series mapping table between MIWU groups and interrupts */
/Zephyr-latest/dts/bindings/espi/
Dnuvoton,npcx-espi-vw-conf.yaml11 MIWU
/Zephyr-latest/dts/arm/nuvoton/
Dnpcx9m7fb.dtsi45 * Raising the interrupt priority of the MIWU group, which owns SHI CS, to the same as
/Zephyr-latest/drivers/gpio/
Dgpio_npcx.c340 /* Call MIWU routine to setup interrupt configuration */ in gpio_npcx_pin_interrupt_configure()
344 LOG_ERR("Configure MIWU interrupt failed"); in gpio_npcx_pin_interrupt_configure()
367 /* Has the IO pin valid MIWU input source? */ in gpio_npcx_manage_callback()
378 /* Insert or remove a IO callback which being called in MIWU ISRs */ in gpio_npcx_manage_callback()
/Zephyr-latest/soc/nuvoton/npcx/npcx7/
Dsoc.h18 /* NPCX7 MIWU multi-registers offset */
/Zephyr-latest/soc/nuvoton/npcx/npcx9/
Dsoc.h18 /* NPCX9 MIWU multi-registers */
/Zephyr-latest/soc/nuvoton/npcx/npcx4/
Dsoc.h18 /* NPCX4 MIWU multi-registers */

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