1 /* 2 * Copyright (c) 2020 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _NUVOTON_NPCX_SOC_H_ 8 #define _NUVOTON_NPCX_SOC_H_ 9 10 #include <cmsis_core_m_defaults.h> 11 12 /* NPCX7 SCFG multi-registers offset */ 13 #define NPCX_DEVALT_OFFSET(n) (0x010 + n) 14 #define NPCX_PUPD_EN_OFFSET(n) (0x028 + n) 15 #define NPCX_LV_GPIO_CTL_OFFSET(n) ((n < 5) ? (0x02a + n) : (0x021 + n)) 16 #define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n) 17 18 /* NPCX7 MIWU multi-registers offset */ 19 #define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 2) + ((n < 5) ? 0 : 0x01e)) 20 #define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 2) + ((n < 5) ? 0 : 0x01e)) 21 #define NPCX_WKMOD_OFFSET(n) (0x070 + n) 22 #define NPCX_WKPND_OFFSET(n) (0x00a + (n * 4) + ((n < 5) ? 0 : 0x010)) 23 #define NPCX_WKPCL_OFFSET(n) (0x00c + (n * 4) + ((n < 5) ? 0 : 0x010)) 24 #define NPCX_WKEN_OFFSET(n) (0x01e + (n * 2) + ((n < 5) ? 0 : 0x012)) 25 #define NPCX_WKINEN_OFFSET(n) (0x01f + (n * 2) + ((n < 5) ? 0 : 0x012)) 26 27 /* NPCX7 ADC multi-registers offset */ 28 #define NPCX_CHNDAT_OFFSET(n) (0x040 + (n * 2)) 29 #define NPCX_THRCTL_OFFSET(n) (0x014 + (n * 2)) 30 31 /* NPCX7 ADC register fields */ 32 #define NPCX_THRCTL_THEN 15 33 #define NPCX_THRCTL_L_H 14 34 #define NPCX_THRCTL_CHNSEL FIELD(10, 4) 35 #define NPCX_THRCTL_THRVAL FIELD(0, 10) 36 37 /* NPCX7 supported group mask of DEVALT_LK */ 38 #define NPCX_DEVALT_LK_GROUP_MASK \ 39 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | \ 40 BIT(6) | BIT(11) | BIT(15)) /* DEVALT0_LK - DEVALTF_LK */ 41 42 /* NPCX7 Clock configuration */ 43 #define MAX_OFMCLK 100000000 44 45 #include <reg/reg_access.h> 46 #include <reg/reg_def.h> 47 #include <soc_dt.h> 48 #include <soc_clock.h> 49 #include <soc_pins.h> 50 #include <soc_power.h> 51 52 #endif /* _NUVOTON_NPCX_SOC_H_ */ 53
