Home
last modified time | relevance | path

Searched full:mclk (Results 1 – 25 of 70) sorted by relevance

123

/Zephyr-latest/soc/atmel/sam0/common/
Dsercom_fixup_samd5x.h8 #define MCLK_SERCOM0 (&MCLK->APBAMASK.reg)
12 #define MCLK_SERCOM0 (&MCLK->APBBMASK.reg)
16 #define MCLK_SERCOM0 (&MCLK->APBCMASK.reg)
20 #define MCLK_SERCOM0 (&MCLK->APBDMASK.reg)
25 #define MCLK_SERCOM1 (&MCLK->APBAMASK.reg)
29 #define MCLK_SERCOM1 (&MCLK->APBBMASK.reg)
33 #define MCLK_SERCOM1 (&MCLK->APBCMASK.reg)
37 #define MCLK_SERCOM1 (&MCLK->APBDMASK.reg)
42 #define MCLK_SERCOM2 (&MCLK->APBAMASK.reg)
46 #define MCLK_SERCOM2 (&MCLK->APBBMASK.reg)
[all …]
Dtc_fixup_samd5x.h8 #define MCLK_TC0 (&MCLK->APBAMASK.reg)
12 #define MCLK_TC0 (&MCLK->APBBMASK.reg)
16 #define MCLK_TC0 (&MCLK->APBCMASK.reg)
20 #define MCLK_TC0 (&MCLK->APBDMASK.reg)
25 #define MCLK_TC2 (&MCLK->APBAMASK.reg)
29 #define MCLK_TC2 (&MCLK->APBBMASK.reg)
33 #define MCLK_TC2 (&MCLK->APBCMASK.reg)
37 #define MCLK_TC2 (&MCLK->APBDMASK.reg)
42 #define MCLK_TC4 (&MCLK->APBAMASK.reg)
46 #define MCLK_TC4 (&MCLK->APBBMASK.reg)
[all …]
Dgmac_fixup_samd5x.h13 #define MCLK_GMAC (&MCLK->APBAMASK.reg)
17 #define MCLK_GMAC (&MCLK->APBBMASK.reg)
21 #define MCLK_GMAC (&MCLK->APBCMASK.reg)
25 #define MCLK_GMAC (&MCLK->APBDMASK.reg)
Datmel_sam0_dt.h15 /* Helper macro to get MCLK register address for corresponding
19 (DT_REG_ADDR(DT_INST_PHANDLE_BY_NAME(n, clocks, mclk)) + \
20 DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, offset))
Dadc_fixup_sam0.h75 #if defined(MCLK)
109 * The following MCLK clock configuration fix-up symbols map to the applicable
114 # define MCLK_ADC (MCLK->APBDMASK.reg)
116 # define MCLK_ADC (MCLK->APBCMASK.reg)
120 #endif /* MCLK */
/Zephyr-latest/dts/arm/atmel/
Dsaml21.dtsi22 clocks = <&gclk 25>, <&mclk 0x1c 5>;
23 clock-names = "GCLK", "MCLK";
34 clocks = <&gclk 25>, <&mclk 0x1c 6>;
35 clock-names = "GCLK", "MCLK";
46 clocks = <&gclk 26>, <&mclk 0x1c 7>;
47 clock-names = "GCLK", "MCLK";
58 clocks = <&gclk 32>, <&mclk 0x1c 12>;
59 clock-names = "GCLK", "MCLK";
64 clocks = <&gclk 18>, <&mclk 0x1c 0>;
65 clock-names = "GCLK", "MCLK";
[all …]
Dsamc21.dtsi23 clocks = <&gclk 34>, <&mclk 0x1c 18>;
24 clock-names = "GCLK", "MCLK";
37 clocks = <&gclk 23>, <&mclk 0x1c 5>;
38 clock-names = "GCLK", "MCLK";
46 clocks = <&gclk 25>, <&mclk 0x1c 6>;
47 clock-names = "GCLK", "MCLK";
56 clocks = <&gclk 26>, <&mclk 0x10 8>;
57 clock-names = "GCLK", "MCLK";
69 clocks = <&gclk 27>, <&mclk 0x10 9>;
70 clock-names = "GCLK", "MCLK";
Dsamd5x.dtsi90 mclk: mclk@40000800 { label
91 compatible = "atmel,samd5x-mclk";
169 clocks = <&gclk 7>, <&mclk 0x14 12>;
170 clock-names = "GCLK", "MCLK";
178 clocks = <&gclk 8>, <&mclk 0x14 13>;
179 clock-names = "GCLK", "MCLK";
187 clocks = <&gclk 23>, <&mclk 0x18 9>;
188 clock-names = "GCLK", "MCLK";
196 clocks = <&gclk 24>, <&mclk 0x18 10>;
197 clock-names = "GCLK", "MCLK";
[all …]
Dsamc2x.dtsi80 mclk: mclk@40000800 { label
81 compatible = "atmel,samc2x-mclk";
125 clocks = <&gclk 33>, <&mclk 0x1c 17>;
126 clock-names = "GCLK", "MCLK";
139 clocks = <&gclk 19>, <&mclk 0x1c 1>;
140 clock-names = "GCLK", "MCLK";
148 clocks = <&gclk 20>, <&mclk 0x1c 2>;
149 clock-names = "GCLK", "MCLK";
157 clocks = <&gclk 21>, <&mclk 0x1c 3>;
158 clock-names = "GCLK", "MCLK";
[all …]
Dsame5x.dtsi37 clocks = <&gclk 27>, <&mclk 0x10 17>;
38 clock-names = "GCLK", "MCLK";
50 clocks = <&gclk 28>, <&mclk 0x10 18>;
51 clock-names = "GCLK", "MCLK";
/Zephyr-latest/dts/bindings/audio/
Dwolfson,wm8904.yaml15 default: "MCLK"
19 - "MCLK": WM8904's MCLK pin (supplied by the host)
21 The "MCLK" option is default, as this clock signal is usually supplied
24 - "MCLK"
/Zephyr-latest/drivers/pwm/
Dpwm_sam0_tcc.c29 #ifdef MCLK
30 volatile uint32_t *mclk; member
110 #ifdef MCLK in pwm_sam0_init()
113 *cfg->mclk |= cfg->mclk_mask; in pwm_sam0_init()
143 #ifdef MCLK
145 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(inst), \
146 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, mclk, bit)), \
Dpwm_sam0_tc.c40 #ifdef MCLK
41 volatile uint32_t *mclk; member
141 #ifdef MCLK in pwm_sam0_init()
144 *cfg->mclk |= cfg->mclk_mask; in pwm_sam0_init()
188 #ifdef MCLK
190 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(inst), \
191 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, mclk, bit)), \
/Zephyr-latest/dts/bindings/clock/
Datmel,samc2x-mclk.yaml4 description: Atmel SAMC2x Generic Clock Controller (MCLK)
6 compatible: "atmel,samc2x-mclk"
Datmel,samd5x-mclk.yaml4 description: Atmel SAMD5x Generic Clock Controller (MCLK)
6 compatible: "atmel,samd5x-mclk"
Datmel,saml2x-mclk.yaml4 description: Atmel SAML2x Generic Clock Controller (MCLK)
6 compatible: "atmel,saml2x-mclk"
Dnuvoton,npcm-pcc.yaml61 dividing OFMCLK(MCLK) and needs to meet the following requirements.
62 - The maximum CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
91 OFMCLK(MCLK) and needs to meet the following requirements.
92 - The maximum APB1_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
121 OFMCLK(MCLK) and needs to meet the following requirements.
122 - The maximum APB2_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
151 OFMCLK(MCLK) and needs to meet the following requirements.
152 - The maximum APB3_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
Dnuvoton,npcx-pcc.yaml58 dividing OFMCLK(MCLK) and needs to meet the following requirements.
88 OFMCLK(MCLK) and needs to meet the following requirements.
119 OFMCLK(MCLK) and needs to meet the following requirements.
150 OFMCLK(MCLK) and needs to meet the following requirements.
180 OFMCLK(MCLK) and needs to meet the following requirements.
/Zephyr-latest/drivers/dai/intel/ssp/
Ddai-params-intel-ipc3.h83 /* mclk 0 disable */
85 /* mclk 1 disable */
87 /* mclk keep active */
95 /* mclk early start */
106 uint32_t mclk_rate; /* mclk frequency in Hz */
120 /* MCLK */
Dssp_regs_v1.h224 /** \brief Offset of MCLK Divider Control Register. */
227 /** \brief Offset of MCLK Divider x Ratio Register. */
234 /** \brief Enables the output of MCLK Divider. */
237 /** \brief Bits for setting MCLK source clock. */
249 /** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */
Dssp_regs_v2.h226 /** \brief Offset of MCLK Divider Control Register. */
229 /** \brief Offset of MCLK Divider x Ratio Register. */
232 /** \brief Enables the output of MCLK Divider. */
235 /** \brief Bits for setting MCLK source clock. */
247 /** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */
/Zephyr-latest/dts/bindings/dai/
Dnxp,dai-sai.yaml13 mclk-is-output:
16 Use this property to set the SAI MCLK as output or as input.
17 By default, if this property is not specified, MCLK will be
18 set as input. Setting the MCLK as output for SAIs which don't
19 support MCLK configuration will result in a BUILD_ASSERT()
/Zephyr-latest/drivers/counter/
Dcounter_sam0_tc32.c34 #ifdef MCLK
35 volatile uint32_t *mclk; member
339 #ifdef MCLK in counter_sam0_tc32_initialize()
344 /* Enable TC clock in MCLK */ in counter_sam0_tc32_initialize()
345 *cfg->mclk |= cfg->mclk_mask; in counter_sam0_tc32_initialize()
406 #ifdef MCLK
408 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
409 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
/Zephyr-latest/drivers/can/
Dcan_sam0.c27 volatile uint32_t *mclk; member
129 /* Enable CAN clock in MCLK */ in can_sam0_clock_enable()
130 *cfg->mclk |= cfg->mclk_mask; in can_sam0_clock_enable()
214 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(inst), \
215 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, mclk, bit)), \
/Zephyr-latest/drivers/entropy/
Dentropy_sam.c152 #ifdef MCLK in entropy_sam_init()
153 /* Enable the MCLK */ in entropy_sam_init()
154 MCLK->APBCMASK.bit.TRNG_ = 1; in entropy_sam_init()

123