Searched full:hsync (Results 1 – 25 of 42) sorted by relevance
12
| /Zephyr-latest/dts/bindings/display/panel/ |
| D | panel-timing.yaml | 14 hsync-len = <8>;
20 hsync-active = <0>;
36 (width + hsync-len + hfront-porch + hback-porch) *
39 hsync-len:
79 hsync-active:
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| /Zephyr-latest/dts/bindings/video/ |
| D | st,stm32-dcmi.yaml | 19 hsync-active = <0>;
59 hsync-active:
71 When HSYNC is low, the data is valid.
72 When HSYNC is high, the data is not valid (horizontal blanking).
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| D | nxp,video-smartdma.yaml | 20 hsync-pin:
24 GPIO0 pin index to use for HSYNC input. Only pins 0-15 may be used.
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| D | espressif,esp32-cam.yaml | 40 invert-hsync:
42 description: invert hsync signal
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| D | video-interfaces.yaml | 88 hsync-active:
94 Active state of the HSYNC signal
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| /Zephyr-latest/boards/shields/rk055hdmipi4m/ |
| D | rk055hdmipi4m.overlay | 44 hsync-len = <8>;
50 hsync-active = <0>;
57 * (width + hsync-len + hfront-porch + hback-porch) * frame rate
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| /Zephyr-latest/boards/shields/rk055hdmipi4ma0/ |
| D | rk055hdmipi4ma0.overlay | 44 hsync-len = <6>;
50 hsync-active = <0>;
57 * (width + hsync-len + hfront-porch + hback-porch) * frame rate
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| /Zephyr-latest/boards/shields/rk043fn02h_ct/ |
| D | rk043fn02h_ct.overlay | 36 hsync-len = <41>;
44 hsync-active = <0>;
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| /Zephyr-latest/boards/shields/rk043fn66hs_ctg/ |
| D | rk043fn66hs_ctg.overlay | 37 hsync-len = <4>;
45 hsync-active = <0>;
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| /Zephyr-latest/boards/shields/rtkmipilcdb00000be/ |
| D | rtkmipilcdb00000be.overlay | 51 hsync-len = <2>;
55 hsync-active = <0>;
|
| /Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/ |
| D | st_b_lcd40_dsi1_mb1166.overlay | 45 hsync-active = <0>;
49 hsync-len = <2>;
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| D | st_b_lcd40_dsi1_mb1166_a09.overlay | 45 hsync-active = <0>;
49 hsync-len = <2>;
|
| /Zephyr-latest/boards/renesas/da1469x_dk_pro/dts/ |
| D | da1469x_dk_pro_lcdc.overlay | 70 hsync-len = <2>;
76 hsync-active = <0>;
|
| /Zephyr-latest/dts/bindings/display/ |
| D | ftdi,ft800.yaml | 100 description: Number of PCLK cycles of HSYNC high state during start of
106 description: Number of PCLK cycles for HSYNC toggle during start of line.
|
| /Zephyr-latest/dts/bindings/gpio/ |
| D | nxp,parallel-lcd-connector.yaml | 26 32 LCD HSYNC
|
| /Zephyr-latest/boards/shields/weact_ov2640_cam_module/ |
| D | weact_ov2640_cam_module.overlay | 34 hsync-active = <0>;
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | mipi_dsi.h | 42 uint32_t hsync; member
66 /** Enable hsync-end packets in vsync-pulse and v-porch area */
72 /** Disable hsync-active area */
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| /Zephyr-latest/boards/st/stm32f746g_disco/ |
| D | stm32f746g_disco.dts | 276 hsync-active = <0>;
278 hsync-len = <1>;
|
| /Zephyr-latest/boards/st/stm32f429i_disc1/ |
| D | stm32f429i_disc1.dts | 249 hsync-active = <0>;
251 hsync-len = <10>;
|
| /Zephyr-latest/boards/st/stm32f7508_dk/ |
| D | stm32f7508_dk.dts | 272 hsync-active = <0>;
274 hsync-len = <1>;
|
| /Zephyr-latest/boards/st/stm32h750b_dk/ |
| D | stm32h750b_dk.dts | 106 hsync-active = <0>;
108 hsync-len = <1>;
|
| /Zephyr-latest/boards/st/stm32h7b3i_dk/ |
| D | stm32h7b3i_dk.dts | 236 hsync-active = <0>;
238 hsync-len = <1>;
|
| /Zephyr-latest/boards/witte/linum/ |
| D | linum.dts | 324 hsync-active = <0>;
326 hsync-len = <1>;
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| /Zephyr-latest/drivers/display/ |
| D | display_hx8394.c | 183 * falling edge in multiples of HSYNC
204 0x4B, /* CHP0 = 4x hsync, CCP0 = 0xB */
206 0x7, /* CHR1_GS = 9x hsync */
207 0x7, /* CHP1 = 1x hsync, CCP1 = 0x7 */
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| /Zephyr-latest/boards/shields/dvp_fpc24_mt9m114/doc/ |
| D | index.rst | 35 | 9 | Hsync |
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