Searched full:cpu2 (Results 1 – 25 of 32) sorted by relevance
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32wl-rcc.yaml | 14 - cpu2-prescaler
17 cpu2-prescaler:
31 CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2.
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| D | st,stm32wb-rcc.yaml | 39 cpu2-prescaler:
54 CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2.
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| D | st,stm32h7-rcc.yaml | 64 D2 domain, CPU2 core clock and AHB(1/2/3/4) peripheral prescaler
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| /Zephyr-latest/soc/nxp/rw/ |
| D | sections.ld | 28 /* CPU3 <-> CPU2 mailbox */
31 /* Reserve space for CPU1 -> CPU3 TXQ (allocated by the CPU2) */
33 /* CPU3 -> CPU2 TXQ */
36 /* Left space is reserved for CPU3/CPU2 operations */
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| /Zephyr-latest/drivers/flash/ |
| D | flash_stm32wbx.c | 99 * When the PESD bit mechanism is used by CPU2 to protect its in write_dword()
107 * used to protect the CPU2 timing. in write_dword()
134 * Check now if the CPU2 disallows flash processing to in write_dword()
136 * CPU2 does not allow flash processing in write_dword()
138 * Note: By default, the CPU2 uses the PESD mechanism in write_dword()
144 * The protection by semaphore is enabled on CPU2 side in write_dword()
173 * opportunity to CPU2 to protect its timing in write_dword()
176 * Note that the CPU2 is polling on this in write_dword()
236 * When the PESD bit mechanism is used by CPU2 to protect its in erase_page()
244 * used to protect the CPU2 timing. in erase_page()
[all …]
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| /Zephyr-latest/soc/st/stm32/common/ |
| D | stm32_hsem.h | 18 * Index of the semaphore used by CPU2 to prevent the CPU1 to either write or
20 * this semaphore is taken by the CPU2. When the CPU1 needs to either write or
23 * On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and
24 * CPU2 is using PES bit. By default, CPU2 is using the PES bit to protect its
25 * timing. The CPU1 may request the CPU2 to use the semaphore instead of the
31 * Index of the semaphore used by CPU1 to prevent the CPU2 to either write or
33 * semaphore to prevent the CPU2 to either write or erase in flash
35 * The PES bit shall not be used as this may stall the CPU2 in some cases.
75 /** Index of the semaphore for CPU2 mailbox */
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| /Zephyr-latest/boards/snps/hsdk/support/ |
| D | openocd-2-cores.cfg | 48 set _TARGETNAME2 $_CHIPNAME.cpu2
49 jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
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| D | openocd.cfg | 48 set _TARGETNAME2 $_CHIPNAME.cpu2
49 jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
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| /Zephyr-latest/tests/kernel/smp_boot_delay/src/ |
| D | main.c | 110 zassert_false(mp_flag, "CPU2 must not be running yet"); in ZTEST()
117 zassert_true(mp_flag, "CPU2 did not start"); in ZTEST()
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| /Zephyr-latest/boards/snps/hsdk4xd/support/ |
| D | openocd.cfg | 48 set _TARGETNAME2 $_CHIPNAME.cpu2
49 jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x100454b1
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | wb_i2c1_sysclk_lptim1_lsi.overlay | 66 cpu2-prescaler = <1>;
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| D | wb_i2c1_hsi_lptim1_lse.overlay | 66 cpu2-prescaler = <1>;
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| D | wl_i2c1_sysclk_lptim1_lsi.overlay | 63 cpu2-prescaler = <1>;
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| D | wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 77 cpu2-prescaler = <1>;
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| /Zephyr-latest/boards/st/stm32wb5mmg/ |
| D | stm32wb5mmg.dts | 49 cpu2-prescaler = <1>;
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| /Zephyr-latest/boards/st/stm32wb5mm_dk/ |
| D | stm32wb5mm_dk.dts | 90 cpu2-prescaler = <1>;
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| /Zephyr-latest/dts/arm64/intel/ |
| D | intel_socfpga_agilex.dtsi | 30 cpu2: cpu@2 { label
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| /Zephyr-latest/boards/st/nucleo_wl55jc/ |
| D | nucleo_wl55jc.dts | 105 cpu2-prescaler = <1>;
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| /Zephyr-latest/dts/riscv/sifive/ |
| D | riscv64-fu740.dtsi | 62 cpu2: cpu@2 { label
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| /Zephyr-latest/boards/st/nucleo_wb55rg/ |
| D | nucleo_wb55rg.dts | 108 cpu2-prescaler = <1>;
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| /Zephyr-latest/boards/arduino/opta/doc/ |
| D | index.rst | 134 as well as by the main PLL clock. By default, the CPU2 (Cortex-M4) System clock
171 - CPU2 (Cortex-M4) boot address is set to 0x08180000
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| /Zephyr-latest/boards/st/stm32h747i_disco/doc/ |
| D | index.rst | 120 is driven by the PLL clock at 400MHz, and the CPU2 (Cortex-M4) System clock
239 - CPU2 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0)
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| /Zephyr-latest/drivers/bluetooth/hci/ |
| D | hci_nxp.c | 465 /* After send annex55 to CPU2, CPU2 need reset, in bt_nxp_setup()
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| /Zephyr-latest/dts/riscv/andes/ |
| D | andes_v5_ae350.dtsi | 52 cpu2: cpu@2 { label
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| /Zephyr-latest/boards/acrn/acrn/doc/ |
| D | index.rst | 157 VM1's configuration so it runs on CPU2 and CPU3. If your ACRN setup has
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