1/*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#define TXQ23_SIZE  0x1080
8#define SMU1_SIZE   DT_REG_SIZE(DT_NODELABEL(smu1_data))
9#define SMU2_SIZE   DT_REG_SIZE(DT_NODELABEL(smu2_data))
10
11
12.SMU1 (NOLOAD) :
13{
14    . = ALIGN(4);
15    /* CPU3 <-> CPU1 mailbox */
16    *(.smu_cpu13_mbox)
17    KEEP (*(.smu_cpu13_mbox))
18    /* CPU3 -> CPU1 TXQ */
19    *(.smu_cpu31_txq)
20    KEEP (*(.smu_cpu31_txq))
21    /* Left space is reserved for CPU3/CPU1 operations */
22    . += SMU1_SIZE - .;
23} > SMU1
24
25.SMU2 (NOLOAD) :
26{
27    . = ALIGN(4);
28    /* CPU3 <-> CPU2 mailbox */
29    *(.smu_cpu23_mbox)
30    KEEP (*(.smu_cpu23_mbox))
31    /* Reserve space for CPU1 -> CPU3 TXQ (allocated by the CPU2) */
32    . += TXQ23_SIZE;
33    /* CPU3 -> CPU2 TXQ */
34    *(.smu_cpu32_txq)
35    KEEP (*(.smu_cpu32_txq))
36    /* Left space is reserved for CPU3/CPU2 operations */
37    . += SMU2_SIZE - .;
38} > SMU2
39