| /Zephyr-latest/subsys/bluetooth/controller/ |
| D | Kconfig.df | 273 prompt "IQ samples 12 bit to 8 bit conversion approach"
278 bool "Conversion of IQ samples to 8 bits wide by 4 bits shift"
282 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
284 8 bits by ordinary right shift operation by 4 bits. That means there is loss in accuracy
285 since only the 8 MSB are used.
288 bool "Conversion of IQ samples to 8 bits wide by 2 bits shift"
292 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
294 8 bits by ordinary right shift operation by 2 bits and a cast to int8_t. That means there
299 bool "Conversion of IQ samples to 8 bits wide by use of 8 LSB"
303 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
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| /Zephyr-latest/dts/bindings/dma/ |
| D | andestech,atcdmac300.yaml | 47 0x0: Byte (8 bits)
48 0x1: Half-word (16 bits)
49 0x2: Word (32 bits)
50 0x3: Double word (64 bits)
51 0x4: Quad word (128 bits)
52 0x5: Eight word (256 bits)
55 0x0: Byte (8 bits)
56 0x1: Half-word (16 bits)
57 0x2: Word (32 bits)
58 0x3: Double word (64 bits)
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| D | gd,gd32-dma-v1.yaml | 27 - 0x0: 8 bits
28 - 0x1: 16 bits
29 - 0x2: 32 bits
33 - 0x0: 8 bits
34 - 0x1: 16 bits
35 - 0x2: 32 bits
82 For example, In the case of data-width is 'byte' and burst-length is 8.
83 If the fifo-threshold is a 2-word case, it runs one burst transfer to transfer 8 bytes.
84 Or the fifo-threshold is a 4-word case, runs two times burst transfer to transferring 8 bytes each
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| D | st,stm32-bdma.yaml | 8 capable of supporting 5 or 6 or 7 or 8 independent BDMA channels.
9 Each channel can have up to 8 requests.
29 0x0: Byte (8 bits)
30 0x1: Half-word (16 bits)
31 0x2: Word (32 bits)
34 0x0: Byte (8 bits)
35 0x1: Half-word (16 bits)
36 0x2: Word (32 bits)
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| D | st,stm32u5-dma.yaml | 21 2. slot: DMA periph request ID, which is written in the REQSEL bits of the CxTR2
37 0x0: Byte (8 bits)
38 0x1: Half-word (16 bits)
39 0x2: Word (32 bits)
42 0x0: Byte (8 bits)
43 0x1: Half-word (16 bits)
44 0x2: Word (32 bits)
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| D | gd,gd32-dma.yaml | 25 - 0x0: 8 bits
26 - 0x1: 16 bits
27 - 0x2: 32 bits
31 - 0x0: 8 bits
32 - 0x1: 16 bits
33 - 0x2: 32 bits
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| D | st,stm32-dmamux.yaml | 27 0x0: Byte (8 bits)
28 0x1: Half-word (16 bits)
29 0x2: Word (32 bits)
32 0x0: Byte (8 bits)
33 0x1: Half-word (16 bits)
34 0x2: Word (32 bits)
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| D | st,stm32-dma-v2.yaml | 11 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
38 0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits)
39 0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
40 0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
43 0x0: STM32_DMA_MEM_8BITS: Byte (8 bits)
44 0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
45 0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
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| /Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/ |
| D | mchp-xec-ecia.h | 11 * g = bits[0:4], GIRQ number in [8, 26]
12 * gb = bits[12:8], peripheral source bit position [0, 31] in the GIRQ
13 * na = bits[23:16], aggregated GIRQ NVIC number
14 * nd = bits[31:24], direct NVIC number. For sources without a direct
20 (((g) & 0x1f) + (((gb) & 0x1f) << 8) + (((na) & 0xff) << 16) + \
25 #define MCHP_XEC_ECIA_GIRQ_POS(e) (((e) >> 8) & 0x1f)
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| /Zephyr-latest/subsys/bluetooth/controller/util/ |
| D | util.c | 24 * @brief Population count: Count the number of bits set to 1
30 * @param octets_len Must not be bigger than 255/8 = 31 bytes
61 * bits.
64 * - It shall have at least three ones in the least significant 8 bits.
66 * bits.
124 if ((bit_idx < 8) && consecutive_bit) { in util_aa_le32()
131 * significant six bits. in util_aa_le32()
149 if (bit_idx < 8) { in util_aa_le32()
157 if (bit_idx < 8) { in util_aa_le32()
186 * significant 16 bits. in util_aa_le32()
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| /Zephyr-latest/include/zephyr/drivers/mfd/ |
| D | npm1300.h | 47 * @param base Register base address (bits 15..8 of 16-bit address)
48 * @param offset Register offset address (bits 7..0 of 16-bit address)
61 * @param base Register base address (bits 15..8 of 16-bit address)
62 * @param offset Register offset address (bits 7..0 of 16-bit address)
73 * @param base Register base address (bits 15..8 of 16-bit address)
74 * @param offset Register offset address (bits 7..0 of 16-bit address)
85 * @param base Register base address (bits 15..8 of 16-bit address)
86 * @param offset Register offset address (bits 7..0 of 16-bit address)
96 * @brief Update selected bits in npm1300 register
99 * @param base Register base address (bits 15..8 of 16-bit address)
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.multilevel | 23 int "Total number of first level interrupt bits"
25 default 8
27 The number of bits to use of the 32 bit interrupt mask for first
55 range 1 8
64 int "Total number of second level interrupt bits"
66 default 8
68 The number of bits to use of the 32 bit interrupt mask for second
100 range 1 8
118 int "Total number of third level interrupt bits"
120 default 8
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| /Zephyr-latest/dts/bindings/crypto/ |
| D | nordic,nrf-ccm.yaml | 17 length-field-length-8-bits:
21 (8 bits) of the LENGTH field in encrypted/decrypted packets.
22 If not set, only the default length (5 bits) is supported.
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| /Zephyr-latest/include/zephyr/dt-bindings/espi/ |
| D | npcx_espi.h | 11 * index = bits[7:0], Replacement index number
12 * group = bits[11:8], Group number for VWEVMS or VWEVSM
13 * dir = bits[13:12], Direction for controller to target or target to controller
16 (((dir & 0x1) << 12) + ((group & 0xf) << 8) + (index & 0xff))
20 #define ESPI_NPCX_VW_EX_GROUP_NUM(e) (((e) >> 8) & 0xf)
32 #define NPCX_VWEVMS8 8
47 #define NPCX_VWEVSM8 8
60 #define NPCX_VWGPSM8 8
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| /Zephyr-latest/include/zephyr/drivers/misc/ft8xx/ |
| D | ft8xx_common.h | 29 * @brief Write 1 byte (8 bits) to FT8xx memory
37 * @brief Write 2 bytes (16 bits) to FT8xx memory
45 * @brief Write 4 bytes (32 bits) to FT8xx memory
53 * @brief Read 1 byte (8 bits) from FT8xx memory
62 * @brief Read 2 bytes (16 bits) from FT8xx memory
71 * @brief Read 4 bytes (32 bits) from FT8xx memory
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| /Zephyr-latest/subsys/net/ip/ |
| D | 6lo.c | 53 static const uint8_t sa_inline_size_table[] = {16, 8, 2, 0, 0, 8, 2, 0};
59 16, 8, 2, 0, 0, 8, 2, 0, 16, 6, 4, 1, 6
86 if (((iphc >> 8) & NET_6LO_DISPATCH_IPHC_MASK) != in get_ihpc_inlined_size()
244 !memcmp(ctx_6co[i].prefix.s6_addr, addr->s6_addr, 8)) { in get_6lo_context_by_addr()
258 * version: 4 bits, Traffic Class: 8 bits, Flow label: 20 bits
259 * The Traffic Class field in the IPv6 header comprises 6 bits of
260 * Diffserv extension [RFC2474] and 2 bits of Explicit Congestion
379 /* Following 64 bits are 0000:00ff:fe00:XXXX */ in compress_sa()
390 NET_DBG("SAM_01 src 64 bits are inlined"); in compress_sa()
391 /* Remaining 64 bits are in-line */ in compress_sa()
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| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | ssp_regs_v1.h | 29 /* SSCR0 bits */
39 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
40 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
50 /* SSCR1 bits */
90 /* SSR bits */
99 /* SSPSP bits */
104 #define SSPSP_DMYSTRT(x) DAI_INTEL_SSP_SET_BITS(8, 7, x)
120 /* SSTSA bits */
123 #define SSTSA_TXEN BIT(8)
125 /* SSRSA bits */
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| D | ssp_regs_v2.h | 30 /* SSCR0 bits */
40 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
41 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
51 /* SSCR1 bits */
91 /* SSR bits */
100 /* SSPSP bits */
105 #define SSPSP_DMYSTRT(x) DAI_INTEL_SSP_SET_BITS(8, 7, x)
121 /* SSTSA bits */
124 #define SSTSA_TXEN BIT(8)
126 /* SSRSA bits */
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| D | ssp_regs_v3.h | 24 #define I2SIPCMC 8
37 /* SSCR0 bits */
47 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
48 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
61 /* SSCR1 bits */
90 /* SSR bits */
95 /* SSPSP bits */
99 #define SSPSP_DMYSTRT(x) DAI_INTEL_SSP_SET_BITS(8, 7, x)
111 #define SSPSP2_RFAC DAI_INTEL_SSP_MASK(9, 8)
121 /* SSTSA bits */
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| /Zephyr-latest/drivers/fpga/ |
| D | fpga_altera_agilex_bridge.h | 110 /* update number bits */
111 uint32_t update_number : 8;
112 /* minor acds release number bits */
113 uint32_t minor_acds_release_number : 8;
114 /* major acds release number bits */
115 uint32_t major_acds_release_number : 8;
116 /* qspi flash index bits */
117 uint32_t qspi_flash_index : 8;
125 /* msel bits */
127 /* pmf data bits */
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| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | imx_ccm.h | 11 * Define 16 bits clock ID: 0xXXXX
12 * The highest 8 bits is Peripheral ID
13 * The lowest 8 bits is Instance ID
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| /Zephyr-latest/dts/bindings/serial/ |
| D | uart-controller.yaml | 26 stop-bits:
29 Sets the number of stop bits.
35 data-bits:
38 Sets the number of data bits.
43 - 8
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | maxim,max31875.yaml | 29 - "8"
37 The number of bits used for each temperature sample.
38 A resolution of 10 bits takes 35ms to convert.
41 10 bits of resolution is the power-on reset configuration.
47 - 8 # 8.75
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| /Zephyr-latest/drivers/spi/ |
| D | spi_dw.h | 99 case 8: in reg_read()
113 case 8: in reg_write()
179 /* Common registers settings, bits etc... */
185 #define DW_SPI_CTRLR0_TMOD_SHIFT (8)
190 #define DW_SPI_CTRLR0_SCPH_BIT (8)
211 /* 0x38 represents the bits 8, 16 and 32. Knowing that 24 is bits 8 and 16
212 * These are the bits were when you divide by 8, you keep the result as it is.
217 (((__bpw) / 8) + 1) : \
218 ((__bpw) / 8))
220 /* SSIENR bits */
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| /Zephyr-latest/include/zephyr/arch/arm64/ |
| D | tpidrro_el0.h | 9 * @brief tpidrro_el0 bits allocation
12 * CPU's struct _cpu instance. But such a pointer is at least 8-bytes
13 * aligned, and the address space is 48 bits max. That leaves plenty of
14 * free bits for other purposes.
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