Lines Matching +full:8 +full:bits

24 #define I2SIPCMC		8
37 /* SSCR0 bits */
47 #define SSCR0_SCR_MASK		DAI_INTEL_SSP_MASK(19, 8)
48 #define SSCR0_SCR(x)		DAI_INTEL_SSP_SET_BITS(19, 8, x)
61 /* SSCR1 bits */
90 /* SSR bits */
95 /* SSPSP bits */
99 #define SSPSP_DMYSTRT(x)	DAI_INTEL_SSP_SET_BITS(8, 7, x)
111 #define SSPSP2_RFAC		DAI_INTEL_SSP_MASK(9, 8)
121 /* SSTSA bits */
125 /* SSRSA bits */
129 /* SSCR3 bits */
143 /* SSCR4 bits */
146 /* SSCR5 bits */
150 /* SFIFOTT bits */
154 /* SFIFOL bits */
158 #define SSTSA_TSEN			BIT(8)
159 #define SSRSA_RSEN			BIT(8)
162 #define SSCR3_RFL_MASK	DAI_INTEL_SSP_MASK(13, 8)
164 #define SSCR3_RFL_VAL(scr3_val)	(((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0))
232 /** \brief Bits for setting MCLK source clock. */
241 /** \brief Bits for setting M/N source clock. */