Lines Matching +full:8 +full:bits
30 /* SSCR0 bits */
40 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
41 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
51 /* SSCR1 bits */
91 /* SSR bits */
100 /* SSPSP bits */
105 #define SSPSP_DMYSTRT(x) DAI_INTEL_SSP_SET_BITS(8, 7, x)
121 /* SSTSA bits */
124 #define SSTSA_TXEN BIT(8)
126 /* SSRSA bits */
129 #define SSRSA_RXEN BIT(8)
131 /* SSCR3 bits */
145 /* SSCR4 bits */
148 /* SSCR5 bits */
152 /* SFIFOTT bits */
156 /* SFIFOL bits */
160 #define SSTSA_TSEN BIT(8)
161 #define SSRSA_RSEN BIT(8)
164 #define SSCR3_RFL_MASK DAI_INTEL_SSP_MASK(13, 8)
166 #define SSCR3_RFL_VAL(scr3_val) (((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0))
235 /** \brief Bits for setting MCLK source clock. */
244 /** \brief Bits for setting M/N source clock. */