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/Zephyr-latest/dts/bindings/cpu/
Despressif,xtensa-lx6.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz
Despressif,xtensa-lx7.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz (ESP32S2 Only)
Despressif,riscv.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz.
29 description: Value of the external XTAL connected to ESP32. This is typically 40 MHz.
/Zephyr-latest/dts/bindings/clock/
Dmicrochip,xec-pcr.yaml17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
23 default value is 480 for 100 kHz.
43 32KHz clock monitor minimum valid 32KHz period in 48MHz units
49 32KHz clock monitor maximum valid 32KHz period in 48MHz units
Dst,stm32h7-rcc.yaml20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
/Zephyr-latest/boards/shields/lcd_par_s035/
Dlcd_par_s035_8080.overlay40 /* Baud rate on each pin is 1MHz */
44 width = <480>;
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dlpm_rt1064.c228 /* CORE CLK to 600MHz, AHB, IPG to 150MHz, PERCLK to 75MHz */ in clock_full_power()
250 /* Switch to 24MHz core clock, so ARM PLL can power down */ in clock_low_power()
254 /* Switch peripheral mux to 24MHz source */ in clock_low_power()
271 /* CORE CLK to 24MHz and AHB, IPG, PERCLK to 12MHz */ in clock_low_power()
452 /* The target full power frequency for the flexspi clock is ~100MHz. in imxrt_lpm_init()
455 * PFD output frequency formula = (480 * 18) / pfd0_frac in imxrt_lpm_init()
456 * flexspi div formula = FLOOR((480*18) / (pfd0_frac * target_full_power_freq)) in imxrt_lpm_init()
458 flexspi_div = (480 * 18) / (usb1_pll_pfd0_frac * 100); in imxrt_lpm_init()
/Zephyr-latest/soc/atmel/sam/same70/
Dsoc.h78 #define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480)
/Zephyr-latest/soc/atmel/sam/samv71/
Dsoc.h78 #define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480)
/Zephyr-latest/drivers/clock_control/
Dclock_control_ast10x0.c18 #define HPLL_FREQ MHZ(1000)
110 src = MHZ(480); in aspeed_clock_control_get_rate()
140 *rate = MHZ(24) / 13; in aspeed_clock_control_get_rate()
/Zephyr-latest/boards/st/nucleo_h745zi_q/
Dnucleo_h745zi_q_stm32h745xx_m7.dts58 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
74 clock-frequency = <DT_FREQ_M(480)>;
151 /* HSE will be used by default. Uncomment below to enable APB1.2 120MHz clock */
/Zephyr-latest/boards/fanke/fk750m1_vbt6/doc/
Dindex.rst24 - 480 MHz max CPU frequency
27 - Main clock: External 25MHz crystal oscillator.
100 as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 480MHz,
101 driven by an 25MHz external crystal oscillator.
/Zephyr-latest/drivers/video/
Dmt9m114.c87 {0xC808, 4, 0x2DC6C00}, /* CAM_SENSOR_CFG_PIXCLK = 48 Mhz */
128 {MT9M114_CAM_OUTPUT_WIDTH, 2, 0x01E0}, /* 480 */
143 {MT9M114_CAM_CROP_WINDOW_HEIGHT, 2, 0x01E0}, /* 480 */
145 {MT9M114_CAM_OUTPUT_HEIGHT, 2, 0x01E0}, /* 480 */
169 {.width = 480, .height = 272, .params = mt9m114_480_272},
170 {.width = 640, .height = 480, .params = mt9m114_640_480},
181 MT9M114_VIDEO_FORMAT_CAP(480, 272, VIDEO_PIX_FMT_RGB565),
182 MT9M114_VIDEO_FORMAT_CAP(480, 272, VIDEO_PIX_FMT_YUYV),
183 MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_RGB565),
184 MT9M114_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_YUYV),
[all …]
/Zephyr-latest/boards/st/nucleo_h755zi_q/
Dnucleo_h755zi_q_stm32h755xx_m7.dts57 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
73 clock-frequency = <DT_FREQ_M(480)>;
/Zephyr-latest/boards/renesas/ek_ra8m1/doc/
Dindex.rst18 - 480MHz Arm Cortex-M85 based RA8M1 MCU in 224 pins, BGA package
22 providing precision 20.000MHz and 32,768 Hz refeence clocks.
170 * Target Interface Speed: 4 MHz
186 …m/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra8m1-480-mhz-arm-cortex-m85-ba…
/Zephyr-latest/boards/renesas/ek_ra8d1/doc/
Dindex.rst11 of over 3000 Coremark points at 480 MHz and superior graphics capabilities that enable high-resolut…
18 - 480MHz Arm Cortex-M85 based RA8D1 MCU in 224 pins, BGA package
22 providing precision 20.000MHz and 32,768 Hz refeence clocks.
188 * Target Interface Speed: 4 MHz
204 …m/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra8d1-480-mhz-arm-cortex-m85-ba…
/Zephyr-latest/boards/renesas/mck_ra8t1/doc/
Dindex.rst37 - 480MHz Arm Cortex-M85 based RA8T1 MCU in 224 pins, BGA package
39 - MCU input clock: 24MHz (Generate with external crystal oscillator)
163 * Target Interface Speed: 4 MHz
179 …m/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra8t1-480-mhz-arm-cortex-m85-ba…
/Zephyr-latest/boards/st/nucleo_h753zi/
Dnucleo_h753zi.dts75 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
93 div-q = <3>; /* gives 80MHz to the FDCAN */
101 clock-frequency = <DT_FREQ_M(480)>;
/Zephyr-latest/boards/st/stm32h7b3i_dk/
Dstm32h7b3i_dk.dts94 /* PLL1P is used for system clock (280 MHz), PLL1Q is used for FDCAN bit quantum clock (80 MHz) */
105 /* PLL3R is used for outputting 9 MHz pixel clock for LTDC */
229 width = <480>;
/Zephyr-latest/boards/gd/gd32f470i_eval/doc/
Dindex.rst10 to 240 MHz with flash accesses zero wait states, 3072kiB of Flash, 256kiB of
30 - 4.3" LCD (480x272)
/Zephyr-latest/boards/vcc-gnd/yd_stm32h750vb/doc/
Dindex.rst60 is driven by the PLL clock at 480MHz. PLL clock is feed by a 25MHz high speed external clock.
/Zephyr-latest/boards/st/nucleo_h743zi/
Dnucleo_h743zi.dts78 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
96 div-q = <3>; /* gives 80MHz to the FDCAN */
104 clock-frequency = <DT_FREQ_M(480)>;
/Zephyr-latest/boards/st/stm32f7508_dk/doc/
Dindex.rst22 - 4.3-inch 480x272 color LCD-TFT with capacitive touch screen
43 - 216 MHz max CPU frequency
47 - 4.3-inch 480x272 color LCD-TFT with capacitive touch screen
162 clock at 216MHz, driven by a 25MHz high speed external clock.
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c159 /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ in usb_device_clock_init()
215 /* Power on LPOSC (1MHz) */ in rt5xx_clock_init()
221 /* Power on FRO (192MHz or 96MHz) */ in rt5xx_clock_init()
434 /* DMIC source from audio pll, divider 8, 24.576M/8=3.072MHZ in rt5xx_clock_init()
436 * of 3.072MHZ in rt5xx_clock_init()
468 /* RxClkEsc max 60MHz, TxClkEsc 12 to 20MHz. */ in imxrt_pre_init_display_interface()
470 /* RxClkEsc = 192MHz / 4 = 48MHz. */ in imxrt_pre_init_display_interface()
472 /* TxClkEsc = 192MHz / 4 / 3 = 16MHz. */ in imxrt_pre_init_display_interface()
481 * DPHY supports up to 895.1MHz bit clock. in imxrt_pre_init_display_interface()
488 * system pll clock is configured at 528MHz by default. in imxrt_pre_init_display_interface()
/Zephyr-latest/boards/st/nucleo_u5a5zj_q/doc/
Dindex.rst35 They operate at a frequency of up to 160 MHz.
47 - 480 nA Standby mode with RTC
52 - 18.5 µA/MHz Run mode at 3.3 V
59 memories: frequency up to 160 MHz, 240 DMIPS
69 - 1.5 DMIPS/MHz (Drystone 2.1)
70 - 655 CoreMark® (4.09 CoreMark®/MHz)
84 - 16-bit HSPI memory interface up to 160 MHz
104 - 4 to 50 MHz crystal oscillator
106 - Internal 16 MHz factory-trimmed RC (± 1 %)
108 - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one
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