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/Zephyr-latest/dts/bindings/gpio/
Dnxp,cam-44pins-connector.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on NXP 44-pin board-to-board camera connector.
29 44 AF_GND GND 43
31 compatible: "nxp,cam-44pins-connector"
33 include: [gpio-nexus.yaml, base.yaml]
Dsparkfun,micromod-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
12 * An 6-pin Power Supply header. No pins on this header are exposed
17 * 2 i2c buses. Only the corresponding interrupt pin is exposed by
19 * 2 SPI buses not exposed by this binding. Only SPI CS control pin
24 * 12 General purpose pins (G0 - G11).
29 - 00 -> A0 PIN 34
30 - 01 -> A1 PIN 38
31 - 02 -> D0 PIN 10
32 - 03 -> D1/CAM_TRIG PIN 18
33 - 04 -> I2C_INT# PIN 16
[all …]
Dadi,sdp-120.yaml4 # SPDX-License-Identifier: Apache-2.0
9 120-pin SDP interface:
54 44 GPIO2 GPIO3 77
72 compatible: "adi,sdp-120"
74 include: [gpio-nexus.yaml, base.yaml]
/Zephyr-latest/samples/subsys/fs/littlefs/boards/
Dnrf52840dk_nrf52840_spi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &mx25r64;
14 * to provide quad-spi feature. In individual specifications each of the spi
16 * as qspi configuration, which is pin (0,19). That is why spi2 is used here
18 * pin.
21 compatible = "nordic,nrf-spi";
23 cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
24 pinctrl-0 = <&spi2_default>;
25 pinctrl-1 = <&spi2_sleep>;
26 pinctrl-names = "default", "sleep";
[all …]
/Zephyr-latest/tests/drivers/i2c/i2c_target_api/boards/
Dstm32f3_disco.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
6 * Pin Hdr Pin Hdr
8 * i2c2 PA10 P2:43 PA9 P2:44
10 * Short Pin PB7 to PA10, and PB6 to PA9, for the test to pass.
17 compatible = "zephyr,i2c-target-eeprom";
25 compatible = "zephyr,i2c-target-eeprom";
/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
107 /* MIO pin numbers */
152 #define MIO44 44
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
183 #define MIO_GROUP_SPI0_2_SS2_PINS 44
202 #define MIO_GROUP_SDIO0_2_GRP_PINS 40, 41, 42, 43, 44, 45
238 #define MIO_GROUP_CAN1_9_GRP_PINS 44, 45
261 #define MIO_GROUP_UART1_9_GRP_PINS 44, 45
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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dquicklogic-eos-s3-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/dt-util.h>
17 #define QUICKLOGIC_EOS_S3_PINMUX(pin, fun) (pin) (fun) argument
19 #define UART_TX_PAD44 QUICKLOGIC_EOS_S3_PINMUX(44, 0x3)
Dsi32-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
70 #define SI32_SIGNAL_UART1_TX 44
108 * @param pin Port pin number (0 to 15)
110 #define SI32_MUX(fun, port, pin) \ argument
111 ((((port)&0x7)) | (((pin)&0xF) << 3) | ((SI32_SIGNAL_##fun & 0x7F) << 22))
Dsmartbond-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
10 /** Definitions of pin functions */
55 #define SMARTBOND_FUNC_LCD 44
76 #define SMARTBOND_PINMUX(func, port, pin) \ argument
79 (pin) << SMARTBOND_PINMUX_PIN_POS)
Dnrf-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole nRF pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 19-23: Reserved.
15 * - 18: Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only)
16 * - 17: Clockpin enable.
17 * - 16: Pin inversion mode.
18 * - 15: Pin low power mode.
19 * - 14..11: Pin output drive configuration.
20 * - 10..9: Pin pull configuration.
[all …]
/Zephyr-latest/boards/nxp/mimxrt1160_evk/
Dmimxrt1160_evk_mimxrt1166_cm7.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
13 model = "NXP MIMXRT1160-EVK board";
21 zephyr,shell-uart = &lpuart1;
23 zephyr,flash-controller = &is25wp128;
25 zephyr,code-partition = &slot0_partition;
26 zephyr,uart-mcumgr = &lpuart1;
27 zephyr,cpu1-region = &ocram;
32 /* Winbond W9825G6KH-5I */
42 * This node describes the GPIO pins mapping of the 44-pin camera
[all …]
/Zephyr-latest/boards/nxp/mimxrt1170_evk/
Dmimxrt1170_evk_mimxrt1176_cm7.dts2 * Copyright 2021-2022,2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
13 model = "NXP MIMXRT1170-EVK board";
17 mipi-dsi = &mipi_dsi;
26 zephyr,shell-uart = &lpuart1;
28 zephyr,flash-controller = &is25wp128;
30 zephyr,code-partition = &slot0_partition;
31 zephyr,uart-mcumgr = &lpuart1;
32 zephyr,cpu1-region = &ocram;
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dquicklogic,eos-s3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
8 Device pin configuration should be placed in the child nodes of this node.
9 Populate the 'pinmux' field with IO function and pin number.
11 For example, setting pins 44 and 45 for use as UART would look like this:
13 #include <dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
18 input-enable;
22 output-enable;
26 compatible: "quicklogic,eos-s3-pinctrl"
34 child-binding:
40 - name: pincfg-node.yaml
[all …]
/Zephyr-latest/dts/bindings/mipi-dbi/
Drenesas,smartbond-mipi-dbi.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: [mipi-dbi-controller.yaml, pinctrl-device.yaml]
8 compatible: "renesas,smartbond-mipi-dbi"
17 reset-gpios:
18 type: phandle-array
20 Reset GPIO pin. Used to reset the display during initialization.
22 te-enable:
27 te-inversion:
32 dma-prefetch:
35 - "no-prefetch"
[all …]
/Zephyr-latest/samples/boards/ti/cc13x2_cc26x2/system_off/src/
Dext_flash.c5 * SPDX-License-Identifier: Apache-2.0
36 gpio_pin_set(dev, DIO9_PIN, (byte >> (7 - i)) & 0x01); in CC1352R1_LAUNCHXL_sendExtFlashByte()
52 * 3 cycles per loop: 700 loops @ 48 Mhz ~= 44 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
87 printk("%s: device not ready.\n", dev->name); in CC1352R1_LAUNCHXL_shutDownExtFlash()
91 /* Set SPI Flash CS pin as output */ in CC1352R1_LAUNCHXL_shutDownExtFlash()
93 /* Set SPI Flash CLK pin as output */ in CC1352R1_LAUNCHXL_shutDownExtFlash()
95 /* Set SPI Flash MOSI pin as output */ in CC1352R1_LAUNCHXL_shutDownExtFlash()
97 /* Set SPI Flash MISO pin as input */ in CC1352R1_LAUNCHXL_shutDownExtFlash()
/Zephyr-latest/dts/arm/atmel/
Dsam4e.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
19 zephyr,flash-controller = &eefc;
23 #address-cells = <1>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-m4f";
[all …]
/Zephyr-latest/boards/shields/nxp_btb44_ov5640/doc/
Dindex.rst3 NXP BTB-44 OV5640 Camera Module
9 This shield supports ov5640 camera modules which use a 44-pin board-to-board connector and
15 Pins assignment of the NXP board-to-board 44-pin OV5640 camera module
18 +----------------------+--------------------+
19 | Camera Connector Pin | Function |
22 +----------------------+--------------------+
24 +----------------------+--------------------+
26 +----------------------+--------------------+
28 +----------------------+--------------------+
30 +----------------------+--------------------+
[all …]
/Zephyr-latest/samples/bluetooth/encrypted_advertising/
DREADME.rst1 .. zephyr:code-sample:: bluetooth_encrypted_advertising
3 :relevant-api: bluetooth
12 - the exchange of the session key and the initialization vector using the Key
14 - the encryption of advertising payloads,
15 - the decryption of those advertising payloads,
16 - and the update of the Randomizer field whenever the RPA is changed.
29 * Two boards with a push button connected via a GPIO pin, see the :zephyr:code-sample:`button`
38 See :zephyr:code-sample-category:`bluetooth` samples for details.
53 .. code-block:: console
55 *** Booting Zephyr OS build zephyr-v3.3.0-1872-g6fac3c7581dc ***
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg27-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
5 * Pin Control for Silicon Labs XG27 devices
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1) argument
18 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2) argument
19 #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 7, 1, 1, 3) argument
20 #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 7, 1, 2, 4) argument
21 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1) argument
23 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1) argument
24 #define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 19, 1, 1, 3) argument
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/legacy/
Dpsoc6.dtsi3 * Copyright (c) 2020-2021, ATL Electronics
5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include "psoc6-pinctrl.dtsi"
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m0+";
25 compatible = "arm,cortex-m4f";
30 flash-controller@40250000 {
31 compatible = "cypress,psoc6-flash-controller";
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dst-morpho-header.h3 * SPDX-License-Identifier: Apache-2.0
8 /** ST Morpho pin mask (0...143). */
12 * @name ST Morpho pin identifiers
59 #define ST_MORPHO_L_45 44
/Zephyr-latest/boards/st/stm32l562e_dk/
Dstm32l562e_dk_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <st/l5/stm32l562qeixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
12 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
16 compatible = "gpio-leds";
28 compatible = "gpio-keys";
37 die-temp0 = &die_temp;
38 volt-sensor0 = &vref;
39 volt-sensor1 = &vbat;
[all …]
/Zephyr-latest/boards/silabs/dev_kits/sltb004a/
Dsltb004a.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include "sltb004a-pinctrl.dtsi"
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
20 pwm-led0 = &pwm_led0;
29 zephyr,shell-uart = &usart0;
30 zephyr,uart-pipe = &usart0;
36 compatible = "gpio-leds";
48 compatible = "gpio-keys";
64 compatible = "pwm-leds";
[all …]
/Zephyr-latest/dts/x86/intel/
Dapollo_lake.dtsi2 * Copyright (c) 2017-2019 Intel Corporation.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,apollo-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_s32z27x_r52.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/clock/nxp_s32z2_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-r52";
26 compatible = "arm,cortex-r52";
[all …]

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