1/*
2 * Copyright 2021-2022,2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <nxp/nxp_rt11xx_cm7.dtsi>
10#include "mimxrt1170_evk.dtsi"
11
12/ {
13	model = "NXP MIMXRT1170-EVK board";
14	compatible = "nxp,mimxrt1176";
15
16	aliases {
17		mipi-dsi = &mipi_dsi;
18		watchdog0 = &wdog1;
19	};
20
21	chosen {
22		zephyr,sram = &sdram0;
23		zephyr,dtcm = &dtcm;
24		zephyr,itcm = &itcm;
25		zephyr,console = &lpuart1;
26		zephyr,shell-uart = &lpuart1;
27		zephyr,canbus = &flexcan3;
28		zephyr,flash-controller = &is25wp128;
29		zephyr,flash = &is25wp128;
30		zephyr,code-partition = &slot0_partition;
31		zephyr,uart-mcumgr = &lpuart1;
32		zephyr,cpu1-region = &ocram;
33		zephyr,ipc = &mailbox_a;
34	};
35
36	sdram0: memory@80000000 {
37		/* Winbond W9825G6KH-5I */
38		device_type = "memory";
39		reg = <0x80000000 DT_SIZE_M(64)>;
40	};
41
42	/*
43	 * This node describes the GPIO pins of the MIPI FPC interface,
44	 * J48 on the EVK. This interface is standard to several
45	 * NXP EVKs, and is used with several MIPI displays
46	 * (available as zephyr shields)
47	 */
48	nxp_mipi_connector: mipi-connector {
49		compatible = "gpio-nexus";
50		#gpio-cells = <2>;
51		gpio-map-mask = <0xffffffff 0xffffffc0>;
52		gpio-map-pass-thru = <0 0x3f>;
53		gpio-map =	<0  0 &gpio9 29 0>,	/* Pin 1, LEDK */
54				<21 0 &gpio9 1  0>,	/* Pin 21, RESET */
55				<22 0 &gpio9 4  0>,	/* Pin 22, LPTE */
56				<26 0 &gpio6 4  0>,	/* Pin 26, CTP_I2C SDA */
57				<27 0 &gpio6 5  0>,	/* Pin 27, CTP_I2C SCL */
58				<28 0 &gpio9 0  0>,	/* Pin 28, CTP_RST */
59				<29 0 &gpio2 31 0>,	/* Pin 29, CTP_INT */
60				<32 0 &gpio11 16 0>,	/* Pin 32, PWR_EN */
61				<34 0 &gpio9 29 0>;	/* Pin 34, BL_PWM */
62	};
63
64	/*
65	 * This node describes the GPIO pins mapping of the 44-pin camera
66	 * connector, J2 on the EVK. This camera interface is supported
67	 * on several NXP RT11xx EVKs, such as RT1170 and RT1160 EVK and
68	 * is used with an ov5640 camera module available as a Zephyr shield
69	 */
70	nxp_cam_connector: cam-connector {
71		compatible = "nxp,cam-44pins-connector";
72		#gpio-cells = <2>;
73		gpio-map-mask = <0xffffffff 0xffffffc0>;
74		gpio-map-pass-thru = <0 0x3f>;
75		gpio-map =	<9 0 &gpio11 15 0>,	/* Pin 9, RESETB */
76				<17 0 &gpio9 25  0>;	/* Pin 17, PWDN */
77	};
78};
79
80zephyr_lcdif: &lcdif {};
81
82zephyr_mipi_dsi: &mipi_dsi {
83	dphy-ref-frequency = <24000000>;
84};
85
86&lpuart1 {
87	status = "okay";
88	current-speed = <115200>;
89};
90
91&flexcan3 {
92	status = "okay";
93	can-transceiver {
94		max-bitrate = <5000000>;
95	};
96};
97
98&lpspi1 {
99	dmas = <&edma0 0 36>, <&edma0 1 37>;
100	dma-names = "rx", "tx";
101	status = "okay";
102};
103
104nxp_mipi_i2c: &lpi2c5 {
105	pinctrl-0 = <&pinmux_lpi2c5>;
106	pinctrl-names = "default";
107	#address-cells = <1>;
108	#size-cells = <0>;
109};
110
111&lpadc0 {
112	status = "okay";
113};
114
115&usdhc1 {
116	status = "okay";
117	detect-dat3;
118	pwr-gpios = <&gpio10 2 GPIO_ACTIVE_LOW>;
119	sdmmc {
120		compatible = "zephyr,sdmmc-disk";
121		disk-name = "SD";
122		status = "okay";
123	};
124};
125
126&edma0 {
127	status = "okay";
128};
129
130/* GPT and Systick are enabled. If power management is enabled, the GPT
131 * timer will be used instead of systick, as allows the core clock to
132 * be gated.
133 */
134&gpt_hw_timer {
135	status = "okay";
136};
137
138&systick {
139	status = "okay";
140};
141
142&wdog1 {
143	status = "okay";
144};
145
146
147&sai1 {
148	status = "okay";
149};
150
151zephyr_udc0: &usb1 {
152	status = "okay";
153	phy_handle = <&usbphy1>;
154};
155
156&usbphy1 {
157	status = "okay";
158	tx-d-cal = <7>;
159	tx-cal-45-dp-ohms = <6>;
160	tx-cal-45-dm-ohms = <6>;
161};
162
163&mailbox_a {
164	status = "okay";
165};
166
167&pit1 {
168	status = "okay";
169};
170
171&pit2 {
172	status = "okay";
173};
174
175nxp_cam_i2c: &lpi2c6 {};
176
177nxp_mipi_csi: &mipi_csi2rx {};
178
179nxp_csi: &csi {};
180