1/*
2 * Copyright 2021,2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <nxp/nxp_rt11xx_cm7.dtsi>
10#include "mimxrt1160_evk.dtsi"
11
12/ {
13	model = "NXP MIMXRT1160-EVK board";
14	compatible = "nxp,mimxrt1166";
15
16	chosen {
17		zephyr,sram = &sdram0;
18		zephyr,dtcm = &dtcm;
19		zephyr,itcm = &itcm;
20		zephyr,console = &lpuart1;
21		zephyr,shell-uart = &lpuart1;
22		zephyr,canbus = &flexcan3;
23		zephyr,flash-controller = &is25wp128;
24		zephyr,flash = &is25wp128;
25		zephyr,code-partition = &slot0_partition;
26		zephyr,uart-mcumgr = &lpuart1;
27		zephyr,cpu1-region = &ocram;
28		zephyr,ipc = &mailbox_a;
29	};
30
31	sdram0: memory@80000000 {
32		/* Winbond W9825G6KH-5I */
33		device_type = "memory";
34		reg = <0x80000000 DT_SIZE_M(64)>;
35	};
36
37	aliases {
38		watchdog0 = &wdog1;
39	};
40
41	/*
42	 * This node describes the GPIO pins mapping of the 44-pin camera
43	 * connector, J2 on the EVK. This camera interface is supported
44	 * on several NXP RT11xx EVKs, such as RT1170 and RT1160 EVK and
45	 * is used with an ov5640 camera module available as a Zephyr shield
46	 */
47	nxp_cam_connector: cam-connector {
48		compatible = "nxp,cam-44pins-connector";
49		#gpio-cells = <2>;
50		gpio-map-mask = <0xffffffff 0xffffffc0>;
51		gpio-map-pass-thru = <0 0x3f>;
52		gpio-map =	<9 0 &gpio11 15 0>,	/* Pin 9, RESETB */
53				<17 0 &gpio9 25  0>;	/* Pin 17, PWDN */
54	};
55
56	/*
57	 * This node describes the GPIO pins of the MIPI FPC interface,
58	 * J48 on the EVK. This interface is standard to several
59	 * NXP EVKs, and is used with several MIPI displays
60	 * (available as zephyr shields)
61	 */
62	 nxp_mipi_connector: mipi-connector {
63		compatible = "gpio-nexus";
64		#gpio-cells = <2>;
65		gpio-map-mask = <0xffffffff 0xffffffc0>;
66		gpio-map-pass-thru = <0 0x3f>;
67		gpio-map =	<0  0 &gpio9 29 0>,	/* Pin 1, LEDK */
68				<21 0 &gpio9 1  0>,	/* Pin 21, RESET */
69				<22 0 &gpio9 4  0>,	/* Pin 22, LPTE */
70				<26 0 &gpio6 4  0>,	/* Pin 26, CTP_I2C SDA */
71				<27 0 &gpio6 5  0>,	/* Pin 27, CTP_I2C SCL */
72				<28 0 &gpio9 0  0>,	/* Pin 28, CTP_RST */
73				<29 0 &gpio2 31 0>,	/* Pin 29, CTP_INT */
74				<32 0 &gpio11 16 0>,	/* Pin 32, PWR_EN */
75				<34 0 &gpio9 29 0>;	/* Pin 34, BL_PWM */
76	};
77};
78
79&lpuart1 {
80	status = "okay";
81	current-speed = <115200>;
82};
83
84&flexcan3 {
85	status = "okay";
86	can-transceiver {
87		max-bitrate = <5000000>;
88	};
89};
90
91&lpi2c1 {
92	status = "okay";
93};
94
95&lpspi1 {
96	status = "okay";
97};
98
99/* GPT and Systick are enabled. If power management is enabled, the GPT
100 * timer will be used instead of systick, as allows the core clock to
101 * be gated.
102 */
103&gpt_hw_timer {
104	status = "okay";
105};
106
107&systick {
108	status = "okay";
109};
110
111&lpadc0 {
112	status = "okay";
113};
114
115&wdog1 {
116	status = "okay";
117};
118
119&edma0 {
120	status = "okay";
121};
122
123zephyr_udc0: &usb1 {
124	status = "okay";
125};
126
127&mailbox_a {
128	status = "okay";
129};
130
131&pit1 {
132	status = "okay";
133};
134
135&pit2 {
136	status = "okay";
137};
138
139nxp_cam_i2c: &lpi2c6 {};
140
141nxp_mipi_csi: &mipi_csi2rx {};
142
143nxp_csi: &csi {};
144
145zephyr_lcdif: &lcdif {};
146
147zephyr_mipi_dsi: &mipi_dsi {
148	dphy-ref-frequency = <24000000>;
149};
150
151nxp_mipi_i2c: &lpi2c5 {
152	pinctrl-0 = <&pinmux_lpi2c5>;
153	pinctrl-names = "default";
154	#address-cells = <1>;
155	#size-cells = <0>;
156};
157