Home
last modified time | relevance | path

Searched +full:3 +full:mhz (Results 1 – 25 of 598) sorted by relevance

12345678910>>...24

/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35 120000000, 120 MHz
36 100000000, 100 MHz
37 96000000, 96 MHz
38 90000000, 90 MHz
39 80000000, 80 MHz
[all …]
Dnuvoton,npcm-pcc.yaml14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
38 100000000, 100 MHz
39 96000000, 96 MHz
[all …]
Dst,stm32u5-msi-clock.yaml22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
26 - 4 # range 4 around 4 MHz (reset value)
27 - 5 # range 5 around 2 MHz
28 - 6 # range 6 around 1.33 MHz
29 - 7 # range 7 around 1 MHz
30 - 8 # range 8 around 3.072 MHz
31 - 9 # range 9 around 1.536 MHz
[all …]
Dst,stm32-msi-clock.yaml21 - 3 # range 3 around 800 kHz
23 - 5 # range 5 around 2 MHz
24 - 6 # range 6 around 4 MHz (reset value)
25 - 7 # range 7 around 8 MHz
26 - 8 # range 8 around 16 MHz
27 - 9 # range 9 around 24 MHz
28 - 10 # range 10 around 32 MHz
29 - 11 # range 11 around 48 MHz
Dst,stm32l0-pll-clock.yaml8 input frequency from 2 to 24 MHz.
16 The PLL output frequency must not exceed 32 MHz.
36 - 3
45 - 96 MHz when the product is in Range 1
46 - 48 MHz when the product is in Range 2
47 - 24 MHz when the product is in Range 3
49 programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
51 - 3
Dst,stm32l0-msi-clock.yaml24 - 3 # range 3, around 524.288 kHz
25 - 4 # range 4, around 1.048 MHz
26 - 5 # range 5, around 2.097 MHz (reset value)
27 - 6 # range 6, around 4.194 MHz
Dst,stm32c0-hsi-clock.yaml6 On STM32C0, HSI is a 48MHz fixed clock.
12 - 1 ==> HSISYS = 48MHZ
13 - 2 ==> HSISYS = 24MHZ
14 - 4 ==> HSISYS = 12MHZ
15 - 8 ==> HSISYS = 6MHZ
16 - 16 ==> HSISYS = 3MHZ
17 - 32 ==> HSISYS = 1.5MHz
18 - 64 ==> HSISYS = 0.75MHZ
19 - 128 ==> HSISYS = 0.375MHz
/Zephyr-latest/dts/bindings/cpu/
Despressif,xtensa-lx6.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz
26 - 3
Despressif,xtensa-lx7.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz (ESP32S2 Only)
26 - 3
/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h28 #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
40 #define XLNX_GEM_LINK_SPEED_1GBIT 3
57 #define XLNX_GEM_HW_RX_BUFFER_SIZE_8KB 3
/Zephyr-latest/drivers/modem/
DKconfig.hl780079 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
106 Enable Band 5 (850MHz)
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dsoc.c36 #define LOCK_TUNING_FACTORS_OF_LCO BIT(3)
55 pllfreq = MHZ(8); in chip_get_pll_freq()
58 pllfreq = MHZ(16); in chip_get_pll_freq()
61 pllfreq = MHZ(24); in chip_get_pll_freq()
63 case 3: in chip_get_pll_freq()
64 pllfreq = MHZ(32); in chip_get_pll_freq()
67 pllfreq = MHZ(48); in chip_get_pll_freq()
70 pllfreq = MHZ(64); in chip_get_pll_freq()
73 pllfreq = MHZ(72); in chip_get_pll_freq()
76 pllfreq = MHZ(96); in chip_get_pll_freq()
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dti,fdc2x1x.yaml46 The internal clock oscillates at around 43360 KHz (43.36 MHz)
48 Recommended external clock source frequency is 40000 KHz (40 MHz).
83 3 = Perform continuous conversions on Channel 3 (FDC2114, FDC2214 only)
88 - 3
97 1 = 1MHz
98 4 = 3.3MHz
99 5 = 10MHz
100 7 = 33MHz
168 3 = Gain = 16 | Effective Resolution 16 bits | 6.25% full scale
173 - 3
[all …]
/Zephyr-latest/soc/mediatek/mt8xxx/
Dcpuclk.c13 * * power-on default is 26Mhz, confirmed with a hacked SOF that
15 * * The original driver has a 13Mhz mode too, but it doesn't work (it
16 * hits all the same code and data paths as 26MHz and acts as a
41 uint32_t _unused[3];
63 const struct { uint16_t mhz; bool pll; uint32_t pll_con2; } freqs[] = { member
73 * an OS timer driver yet. Use the 13 MHz timer hardware directly.
77 #define TIMER (((volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(ostimer64)))[3])
121 #define SETCLK28(val) setclk(28, 16, 3, 18, (val))
123 void mtk_adsp_set_cpu_freq(int mhz) in mtk_adsp_set_cpu_freq() argument
128 if (freqs[idx].mhz == mhz) { in mtk_adsp_set_cpu_freq()
[all …]
/Zephyr-latest/dts/bindings/i3c/
Dnuvoton,npcx-i3c.yaml11 clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
12 core-prescaler = <3>; /* CORE_CLK runs at 30MHz */
13 apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
14 apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
15 apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
16 apb4-prescaler = <3>; /* APB4_CLK runs at 30MHz */
62 Bit[3:0] port id.
/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dsoc.c63 .preDiv = 3U,
64 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
71 .preDiv = 3U,
72 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
79 .preDiv = 3U,
80 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
88 * to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2 in SOC_ClockInit()
104 /* Set root clock freq to 133M / 1= 133MHZ */ in SOC_ClockInit()
111 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
113 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
[all …]
/Zephyr-latest/soc/atmel/sam/sam4l/
Dsoc.h73 * Internal 80 MHz RC oscillator
74 * Internal 4-8-12 MHz RCFAST oscillator
75 * Internal 1 MHz RC oscillator
81 #define OSC_ID_RC80M 3
91 * 80 MHz RC oscillator
92 * 4-8-12 MHz RC oscillator
93 * 1 MHz RC oscillator
98 #define OSC_SRC_DFLL 3
113 #define PM_CLK_GRP_PBD 3
124 #define SYSCLK_USBC_DATA 3
[all …]
/Zephyr-latest/drivers/spi/
Dspi_esp32_spim.h17 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */
18 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */
19 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */
20 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */
21 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */
22 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */
23 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */
24 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */
25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */
/Zephyr-latest/samples/net/sockets/http_client/
Dieee802154-overlay.conf7 # Uncomment for 868 MHz
9 # Uncomment for 906 MHz:
13 CONFIG_NET_L2_IEEE802154_FRAGMENT_REASS_CACHE_SIZE=3
/Zephyr-latest/samples/net/sockets/http_server/
Dieee802154-overlay.conf7 # Uncomment for 868 MHz
9 # Uncomment for 906 MHz:
13 CONFIG_NET_L2_IEEE802154_FRAGMENT_REASS_CACHE_SIZE=3
/Zephyr-latest/boards/st/stm32g081b_eval/
Dstm32g081b_eval.dts57 gpios = <&gpioc 3 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
141 channel@3 {
142 reg = <3>;
164 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
167 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
168 * range is 9 <--> 18 MHz.
170 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
177 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
179 * 3. tInterframGap - uSec
195 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
[all …]
/Zephyr-latest/soc/gd/gd32/common/
Dpinctrl_soc.h107 /** Maximum 2MHz */
112 /** Maximum 10MHz */
114 /** Maximum 50MHz */
115 #define GD32_OSPEED_50MHZ 3U
117 /** Maximum 25MHz */
119 /** Maximum 50MHz */
122 #define GD32_OSPEED_MAX 3U
126 /** Maximum 10MHz */
128 /** Maximum 2MHz */
130 /** Maximum 50MHz */
[all …]
/Zephyr-latest/samples/boards/ti/cc13x2_cc26x2/system_off/src/
Dext_flash.c42 * 3 cycles per loop: 8 loops @ 48 Mhz = 0.5 us. in CC1352R1_LAUNCHXL_sendExtFlashByte()
52 * 3 cycles per loop: 700 loops @ 48 Mhz ~= 44 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
69 /* 3 cycles per loop: 1 loop @ 48 Mhz ~= 62 ns */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
72 /* 3 cycles per loop: 560 loops @ 48 Mhz ~= 35 us */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
/Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/
Dtestcase.yaml34 extra_args: EXTRA_DTC_OVERLAY_FILE="boards/1mhz.overlay"
40 - CONFIG_TESTED_SPI_MODE=3
41 extra_args: EXTRA_DTC_OVERLAY_FILE="boards/2mhz.overlay"
48 extra_args: EXTRA_DTC_OVERLAY_FILE="boards/4mhz.overlay"
55 extra_args: EXTRA_DTC_OVERLAY_FILE="boards/8mhz.overlay"
/Zephyr-latest/boards/infineon/cy8ckit_062s2_ai/
Dcy8ckit_062s2_ai.dts33 gpios = <&gpio_prt5 3 GPIO_ACTIVE_HIGH>;
61 /* CM4 core clock = 100MHz
62 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
68 /* CM0+ core clock = 50MHz
69 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
75 /* PERI core clock = 100MHz
76 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz

12345678910>>...24