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/Zephyr-latest/soc/atmel/sam0/common/
DKconfig.samd2x19 bool "Internal 8 MHz RC oscillator"
21 Enable the internal 8 MHz RC oscillator at startup.
39 bool "External 0.4..32 MHz clock source"
41 Enable the external 0.4..32 MHz clock source at startup.
45 bool "External 0.4..32 MHz clock is a crystal oscillator"
53 int "External 0.4..32 MHz clock oscillator frequency"
58 External 0.4..32 MHz clock oscillator reference frequency.
/Zephyr-latest/dts/bindings/clock/
Dmicrochip,xec-pcr.yaml17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
25 pll-32k-src:
28 description: 32 KHz clock source for PLL
30 periph-32k-src:
33 description: 32 KHz clock source for peripherals
43 32KHz clock monitor minimum valid 32KHz period in 48MHz units
49 32KHz clock monitor maximum valid 32KHz period in 48MHz units
56 the measured 32KHz high and low pulse widths.
62 Minimum number of consecutive 32KHz pulses that pass all monitor tests
[all …]
Dst,stm32c0-hsi-clock.yaml6 On STM32C0, HSI is a 48MHz fixed clock.
12 - 1 ==> HSISYS = 48MHZ
13 - 2 ==> HSISYS = 24MHZ
14 - 4 ==> HSISYS = 12MHZ
15 - 8 ==> HSISYS = 6MHZ
16 - 16 ==> HSISYS = 3MHZ
17 - 32 ==> HSISYS = 1.5MHz
18 - 64 ==> HSISYS = 0.75MHZ
19 - 128 ==> HSISYS = 0.375MHz
37 - 32
Dst,stm32g0-hsi-clock.yaml6 On STM32G0, HSI is a 16MHz fixed clock.
12 - 1 ==> HSISYS = 16MHZ
13 - 2 ==> HSISYS = 8MHZ
14 - 4 ==> HSISYS = 4MHZ
15 - 8 ==> HSISYS = 2MHZ
16 - 16 ==> HSISYS = 1MHZ
17 - 32 ==> HSISYS = 0.5MHz
18 - 64 ==> HSISYS = 0.25MHZ
19 - 128 ==> HSISYS = 0.125MHz
39 - 32
Dst,stm32l0-pll-clock.yaml8 input frequency from 2 to 24 MHz.
16 The PLL output frequency must not exceed 32 MHz.
45 - 96 MHz when the product is in Range 1
46 - 48 MHz when the product is in Range 2
47 - 24 MHz when the product is in Range 3
49 programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
58 - 32
Dst,stm32h7-hsi-clock.yaml17 - 1 # hsi_clk = 64MHz
18 - 2 # hsi_clk = 32MHz
19 - 4 # hsi_clk = 16MHz
20 - 8 # hsi_clk = 8MHz
Dst,stm32-msi-clock.yaml23 - 5 # range 5 around 2 MHz
24 - 6 # range 6 around 4 MHz (reset value)
25 - 7 # range 7 around 8 MHz
26 - 8 # range 8 around 16 MHz
27 - 9 # range 9 around 24 MHz
28 - 10 # range 10 around 32 MHz
29 - 11 # range 11 around 48 MHz
Despressif,esp32-rtc.yaml21 - 1: ESP32_RTC_FAST_CLK_SRC_RC_FAST - 8 MHz
32 - 1: ESP32_RTC_SLOW_CLK_SRC_XTAL32K - 32,768U KHz
33 - 2: ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 - 17,5 MHz
34 - 9: ESP32_RTC_SLOW_CLK_32K_EXT_OSC - External 32k oscillator connected to 32K_XP pin
/Zephyr-latest/dts/bindings/pwm/
Dmicrochip,xec-pwmbbled.yaml31 Clock source selection: 32 KHz is available in deep sleep.
33 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
47 enable-low-power-32k:
51 - Main system clock (48MHz)
52 - 32KHz Core clock (32.768KHz)
53 When BBLED enter into Suspend state, 48MHz clock will be switched off by
54 PCR(Power, Clock and Reset) block. But 32KHz Core clock will be available to BBLED.
56 Property "enable-low-power-32k" shall be used along with 32KHz clock to blink (or) not blink
/Zephyr-latest/tests/boards/espressif/rtc_clk/
DREADME.rst37 If the external 32K crystal is connect to pins 32K_XP and 32K_XN, the test can be run with ``extern…
55 Testing CPU frequency: 80 MHz
56 Testing CPU frequency: 160 MHz
57 Testing CPU frequency: 240 MHz
61 Testing CPU frequency: 40 MHz
62 Testing CPU frequency: 20 MHz
63 Testing CPU frequency: 10 MHz
64 Testing CPU frequency: 5 MHz
68 Testing RTC FAST CLK freq: 20000000 MHz
69 Testing RTC FAST CLK freq: 17500000 MHz
[all …]
/Zephyr-latest/dts/bindings/i2s/
Dnordic,nrf-i2s.yaml30 - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK
31 - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator
/Zephyr-latest/drivers/ieee802154/
DKconfig.mcr20a33 bool "32 MHz"
36 bool "16 MHz"
39 bool "8 MHz"
42 bool "4 MHz"
45 bool "1 MHz"
/Zephyr-latest/dts/bindings/audio/
Dnordic,nrf-pdm.yaml29 - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK
30 - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Dhse_32.overlay13 clock-frequency = <DT_FREQ_M(32)>; /* 32MHz oscillator */
19 clock-frequency = <DT_FREQ_M(32)>;
/Zephyr-latest/drivers/timer/
DKconfig.mec514 The 32-bit 32 KHz based RTOS timer which is operational in
15 full power and deep sleep. Basic timer 5 is a 48 MHz based
16 32-bit down counter with frequency divider used for the
/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
36 * HW count resolution is 48 MHz.
37 * One 32KHz clock pulse = 1464.84 48 MHz counts.
156 #define XEC_CC_VBATR_CS_XTAL_SE BIT(9) /* crystal XTAL2 used as 32KHz input */
162 /* MEC172x Select source of peripheral 32KHz clock */
168 #define XEC_CC_VBATR_CS_PCS_VTR_PIN_SO 0x20000u /* VTR 32KHZ_IN, VBAT silicon OSC */
169 #define XEC_CC_VBATR_CS_PCS_VTR_PIN_XTAL 0x30000u /* VTR 32KHZ_IN, VBAT XTAL */
[all …]
Dclock_stm32_ll_wb0.c73 /* When using HSI without PLL, the "16MHz" output is not actually 16MHz, since
75 * The CPU and MR_BLE must be running at 32MHz for MR_BLE to work with HSI.
78 "System clock frequency must be at least 32MHz to use LSI");
80 /* In PLL or Direct HSE mode, the clock is stable, so 16MHz can be used. */
82 "System clock frequency must be at least 16MHz to use LSI");
137 * LSI calibration counts the amount of 16MHz clock half-periods that in measure_lsi_frequency()
140 * @p fast_clock_cycles_elapsed is the number of 16MHz clock half-periods in measure_lsi_frequency()
148 * tCALIB = @p fast_clock_cycles_elapsed / (2 * 16MHz) in measure_lsi_frequency()
154 * ( @p fast_clock_cycles_elapsed / (2 * 16MHz) ) in measure_lsi_frequency()
164 * ( @p fast_clock_cycles_elapsed / (2 * 16MHz) ) in measure_lsi_frequency()
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h16 * divider /32 is the reset value. The network_config[mdc_clock_division]
28 #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,mcux-rt-pinctrl.yaml17 nxp,speed = "100-mhz";
22 slow slew rate, and 100 MHZ speed.
98 101 DSE_5_R0_5 — 32 Ohm @3.3V, 52 Ohm @1.8V
99 110 DSE_6_R0_6 — 32 Ohm @3.3V, 43 Ohm @1.8V
142 - "50-mhz"
143 - "100-mhz"
144 - "150-mhz"
145 - "200-mhz"
148 00 SPEED_0_low_50MHz_ — low(50MHz)
149 01 SPEED_1_medium_100MHz_ — medium(100MHz)
[all …]
/Zephyr-latest/boards/st/nucleo_wl55jc/doc/
Dnucleo_wl55jc.rst11 - STM32WL55JC microcontroller multiprotocol LPWAN dual-core 32-bit
12 (Arm® Cortex®-M4/M0+ at 48 MHz) in UFBGA73 package featuring:
15 - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®,
22 - 32 MHz HSE on-board oscillator
55 - Frequency range: 150 MHz to 960 MHz
69 - 32-bit Arm® Cortex®-M4 CPU
72 execution from Flash memory, frequency up to 48 MHz, MPU
74 - 1.25 DMIPS/MHz (Dhrystone 2.1)
76 - 32-bit Arm®Cortex®-M0+ CPU
78 - Frequency up to 48 MHz, MPU
[all …]
/Zephyr-latest/soc/espressif/common/
DKconfig.esptool88 bool "120 MHz"
92 - Flash 120 MHz SDR mode is stable.
93 - Flash 120 MHz DDR mode is an experimental feature, it works when
102 bool "80 MHz"
104 bool "60 MHz"
106 bool "40 MHz"
108 bool "26 MHz"
111 bool "20 MHz"
119 This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed.
150 bool "32 MB"
[all …]
/Zephyr-latest/boards/st/nucleo_u031r8/doc/
Dindex.rst35 Series) based on the high-performance Arm |reg| Cortex |reg|-M0+ 32-bit RISC core.
36 They operate at a frequency of up to 56 MHz.
43 - 130 nA VBAT mode: supply for RTC, 9 x 32-bit backup registers
50 - 52 µA/MHz Run mode
55 - 32-bit Arm |reg| Cortex |reg|-M0+ CPU, frequency up to 56 MHz
63 - 1.13 DMIPS/MHz (Drystone 2.1)
64 - 134 CoreMark |reg| (2.4 CoreMark/MHz at 56 MHz)
80 - 4 to 48 MHz crystal oscillator
81 - 32 kHz crystal oscillator for RTC (LSE)
82 - Internal 16 MHz factory-trimmed RC (±1%)
[all …]
/Zephyr-latest/boards/st/nucleo_l412rb_p/doc/
Dindex.rst28 - 24 MHz HSE
49 - 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers
51 - 32 nA Standby mode (4 wakeup pins)
54 - 79 |micro| A/MHz run mode (LDO Mode)
55 - 28 |micro| A/MHz run mode (@3.3 V SMPS Mode)
61 …32-bit Cortex |reg| -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator |trade| ) al…
64 - 1.25 DMIPS/MHz (Drystone 2.1)
65 - 273.55 CoreMark |reg| (3.42 CoreMark/MHz @ 80 MHz)
74 - 4 to 48 MHz crystal oscillator
75 - 32 kHz crystal oscillator for RTC (LSE)
[all …]
/Zephyr-latest/boards/st/stm32wb5mmg/doc/
Dstm32wb5mmg.rst19 - Frequency band 2402-2480 MHz
25 …ed Arm|reg| Cortex|reg|-M4 CPU with FPU and ART (adaptive real-time accelerator) up to 64 MHz speed
27 - Fully integrated BOM, including 32 MHz radio and 32 kHz RTC crystals
48 - Ultra-low-power with FlexPowerControl (down to 600 nA Standby mode with RTC and 32KB RAM)
49 - Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 64 MHz
66 - Dedicated Arm|reg| 32-bit Cortex|reg| M0+ CPU
77 - 32 MHz crystal oscillator with integrated
79 - 32 kHz crystal oscillator for RTC (LSE)
80 - Internal low-power 32 kHz (±5%) RC (LSI1)
81 - Internal low-power 32 kHz (stability
[all …]
/Zephyr-latest/boards/st/stm32u083c_dk/doc/
Dindex.rst42 Series) based on the high-performance Arm |reg| Cortex |reg|-M0+ 32-bit RISC core.
43 They operate at a frequency of up to 56 MHz.
50 - 130 nA VBAT mode: supply for RTC, 9 x 32-bit backup registers
57 - 52 µA/MHz Run mode (LDO mode)
62 - 32-bit Arm |reg| Cortex |reg|-M0+ CPU, frequency up to 56 MHz
70 - 1.13 DMIPS/MHz (Drystone 2.1)
71 - 134 CoreMark |reg| (2.4 CoreMark/MHz at 56 MHz)
87 - 4 to 48 MHz crystal oscillator
88 - 32 kHz crystal oscillator for RTC (LSE)
89 - Internal 16 MHz factory-trimmed RC (±1%)
[all …]

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