| /Zephyr-latest/dts/bindings/timer/ |
| D | nuclei,systimer.yaml | 30 For example, the CPU clock frequency is 108MHz, and the system timer
31 uses 27MHz, which is the CPU clock divided by 4.
45 that CPU clock frequency divided by (2^2=)4, or 27MHz.
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| /Zephyr-latest/boards/st/stm32g081b_eval/ |
| D | stm32g081b_eval.dts | 164 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
167 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
168 * range is 9 <--> 18 MHz.
170 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
177 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
181 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
186 hbitclkdiv = <27>;
195 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
198 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
199 * range is 9 <--> 18 MHz.
[all …]
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| /Zephyr-latest/drivers/modem/ |
| D | Kconfig.hl7800 | 79 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
106 Enable Band 5 (850MHz)
[all …]
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| /Zephyr-latest/boards/st/b_g474e_dpow1/ |
| D | b_g474e_dpow1.dts | 158 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
161 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
162 * range is 9 <--> 18 MHz.
164 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
171 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
175 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
180 hbitclkdiv = <27>;
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| /Zephyr-latest/boards/st/stm32g071b_disco/ |
| D | stm32g071b_disco.dts | 160 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
163 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
164 * range is 9 <--> 18 MHz.
166 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
173 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
177 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
182 hbitclkdiv = <27>;
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| /Zephyr-latest/soc/gd/gd32/common/ |
| D | pinctrl_soc.h | 107 /** Maximum 2MHz */
112 /** Maximum 10MHz */
114 /** Maximum 50MHz */
117 /** Maximum 25MHz */
119 /** Maximum 50MHz */
126 /** Maximum 10MHz */
128 /** Maximum 2MHz */
130 /** Maximum 50MHz */
146 * - 27..26: Output speed
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| /Zephyr-latest/soc/ti/lm3s6965/ |
| D | soc.h | 23 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(12)
52 #define IRQ_RESERVED0 27
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| /Zephyr-latest/boards/nxp/frdm_mcxn236/ |
| D | board.c | 23 /* Core clock frequency: 150MHz */
77 /* Enable FRO HF(48MHz) output */ in frdm_mcxn236_init()
82 .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | in frdm_mcxn236_init()
103 /* Set up PLL1 for 80 MHz FlexCAN clock */ in frdm_mcxn236_init()
105 .pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(27U) | in frdm_mcxn236_init()
244 /* xtal = 20 ~ 30MHz */ in frdm_mcxn236_init()
277 * 0 <- 12MHz FRO in frdm_mcxn236_init()
289 /* Value here should not exceed 25MHZ when using lptmr */ in frdm_mcxn236_init()
290 CLOCK_SetupExtClocking(MHZ(24)); in frdm_mcxn236_init()
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| /Zephyr-latest/boards/nxp/frdm_mcxn947/ |
| D | board.c | 27 /* Core clock frequency: 150MHz */
102 /* Enable FRO HF(48MHz) output */ in frdm_mcxn947_init()
114 .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | in frdm_mcxn947_init()
135 /* Set up PLL1 for 80 MHz FlexCAN clock */ in frdm_mcxn947_init()
137 .pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(27U) | in frdm_mcxn947_init()
272 /* Drive CLKOUT from main clock, divided by 25 to yield 6MHz clock in frdm_mcxn947_init()
312 /* xtal = 20 ~ 30MHz */ in frdm_mcxn947_init()
342 * 0 <- 12MHz FRO in frdm_mcxn947_init()
354 /* Value here should not exceed 25MHZ when using lptmr */ in frdm_mcxn947_init()
355 CLOCK_SetupExtClocking(MHZ(24)); in frdm_mcxn947_init()
[all …]
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| /Zephyr-latest/boards/pjrc/teensy4/ |
| D | teensy4-pinctrl.dtsi | 20 nxp,speed = "100-mhz";
35 nxp,speed = "200-mhz";
49 nxp,speed = "200-mhz";
60 nxp,speed = "100-mhz";
72 nxp,speed = "100-mhz";
84 nxp,speed = "100-mhz";
97 nxp,speed = "100-mhz";
110 nxp,speed = "100-mhz";
123 nxp,speed = "100-mhz";
128 /* LPSPI3 MISO, MOSI, SCK, CS on Teensy-Pins 39/26/27/38 */
[all …]
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| /Zephyr-latest/drivers/audio/ |
| D | tlv320dac310x.h | 33 #define DAC_PROC_CLK_FREQ_MAX 49152000 /* 49.152 MHz */
41 #define DAC_MOD_CLK_FREQ_MIN 2800000 /* 2.8 MHz */
42 #define DAC_MOD_CLK_FREQ_MAX 6200000 /* 6.2 MHz */
44 #define IF_CTRL1_ADDR (struct reg_addr){0, 27}
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| /Zephyr-latest/include/zephyr/sd/ |
| D | sd_spec.h | 108 SD_R1_ERASE_PARAM = BIT(27),
318 SDIO_OCR_MEM_PRESENT_FLAG = BIT(27), /*!< Memory present flag */
373 HS_MAX_DTR = MHZ(50),
379 UHS_SDR12_MAX_DTR = MHZ(25),
380 UHS_SDR25_MAX_DTR = MHZ(50),
381 UHS_SDR50_MAX_DTR = MHZ(100),
382 UHS_SDR104_MAX_DTR = MHZ(208),
383 UHS_DDR50_MAX_DTR = MHZ(50),
432 SD_CLOCK_25MHZ = MHZ(25),
433 SD_CLOCK_50MHZ = MHZ(50),
[all …]
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| /Zephyr-latest/dts/arm/atmel/ |
| D | saml2x.dtsi | 213 * 16 MHz max, so clock it with the
214 * 48 MHz DFLL / 2 / 2 = 12 MHz
231 interrupts = <27 0>;
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| D | samd5x.dtsi | 136 <24 0>, <25 0>, <26 0>, <27 0>;
321 * 16 MHz max, source clock must not exceed 100 MHz.
324 * -> 48 MHz GCLK(2) / 4 = 12 MHz
343 * 16 MHz max, source clock must not exceed 100 MHz.
346 * -> 48 MHz GCLK(2) / 4 = 12 MHz
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| /Zephyr-latest/boards/adafruit/trinket_m0/doc/ |
| D | index.rst | 6 The Adafruit Trinket M0 is a tiny (27 mm x 15 mm) ARM development
13 - ATSAMD21E18A ARM Cortex-M0+ processor at 48 MHz
15 - Internal trimmed 8 MHz oscillator
63 The SAMD21 MCU is configured to use the 8 MHz internal oscillator
64 with the on-chip PLL generating the 48 MHz system clock. The internal
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| /Zephyr-latest/drivers/sdhc/ |
| D | sdhc_cdns_ll.h | 65 * • 1110b - t_sdmclk*2(27+2)
102 #define CDNS_SRS15_CMD23_EN BIT(27)
146 #define CP_IO_MASK_END(x) ((x) << 27)
460 /* High speed 200Mhz in SDR */
462 /* High speed 200Mhz in DDR */
464 /* High speed 200Mhz in SDR with enhanced strobe */
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| /Zephyr-latest/boards/pine64/pinetime_devkit0/ |
| D | pinetime_devkit0.dts | 57 gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
95 mipi-max-frequency = <8000000>; /* 8MHz */
197 spi-max-frequency = <8000000>; /* 8MHz */
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| /Zephyr-latest/soc/microchip/mec/mec172x/reg/ |
| D | mec172x_pcr.h | 105 * Divides 96MHz clock to ARM Cortex-M4 core including
186 #define MCHP_PCR1_PWM8_POS 27
212 #define MCHP_PCR2_ESPI_SAF_POS 27
327 /* PCR 32KHz clock monitor uses 48 MHz for all counters */
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| /Zephyr-latest/boards/cypress/cy8ckit_062_wifi_bt/doc/ |
| D | index.rst | 14 dual-core MCU, with a 150-MHz Arm Cortex-M4 as the primary application
15 processor and a 100-MHz Arm Cortex-M0+ that supports low-power operations,
56 27. Cypress serial Ferroelectric RAM (U5)1
109 the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the
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| /Zephyr-latest/boards/qemu/cortex_m0/doc/ |
| D | index.rst | 44 This board configuration uses a system clock frequency of 1 MHz.
77 ***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
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| /Zephyr-latest/soc/altr/zephyr_nios2f/cpu/ |
| D | ghrd_10m50da.qsf | 22 # Date created = 16:01:48 April 27, 2016
43 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:01:48 APRIL 27, 2016"
200 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[0]
201 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[2]
202 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_pb[1]
331 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[4]
332 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[1]
333 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[7]
334 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[2]
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| /Zephyr-latest/doc/services/storage/disk/ |
| D | access.rst | 67 at 24 MHz once the SD card has been initialized:
73 cs-gpios = <&porta 27 GPIO_ACTIVE_LOW>;
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| /Zephyr-latest/boards/qemu/cortex_m3/doc/ |
| D | index.rst | 44 This board configuration uses a system clock frequency of 12 MHz.
83 ***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
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| /Zephyr-latest/boards/silabs/dev_kits/sltb004a/doc/ |
| D | index.rst | 13 - EFR32MG12 Mighty Gecko Wireless SoC with 38.4 MHz operating frequency
87 means Pin number 2 on PORTE and #27 represents the location bitfield , as used
105 | PF3 | UART_TX | EXP12_UART_TX LEU0_TX #27 |
107 | PF4 | UART_RX | EXP14_UART_RX LEU0_RX #27 |
129 The EFR32MG12 SoC is configured to use the 38.4 MHz external oscillator on the
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| /Zephyr-latest/soc/nxp/imxrt/imxrt11xx/ |
| D | soc.c | 101 /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
280 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); in clock_init()
413 /* 50 MHz ENET clock */ in clock_init()
430 /* 125 MHz ENET1G clock */ in clock_init()
440 * 50 MHz clock for 10/100Mbit RMII PHY - in clock_init()
459 /* 24MHz PTP clock */ in clock_init()
509 * PLL2 is fixed at 528MHz. Use desired panel clock clock to in clock_init()
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