1.. zephyr:board:: qemu_cortex_m3
2
3Overview
4********
5
6This board configuration will use QEMU to emulate the TI LM3S6965 platform.
7
8This configuration provides support for an ARM Cortex-M3 CPU and these devices:
9
10* Nested Vectored Interrupt Controller
11* System Tick System Clock
12* Stellaris UART
13
14.. note::
15   This board configuration makes no claims about its suitability for use
16   with an actual ti_lm3s6965 hardware system, or any other hardware system.
17
18Hardware
19********
20Supported Features
21==================
22
23The following hardware features are supported:
24
25+--------------+------------+----------------------+
26| Interface    | Controller | Driver/Component     |
27+==============+============+======================+
28| NVIC         | on-chip    | nested vectored      |
29|              |            | interrupt controller |
30+--------------+------------+----------------------+
31| Stellaris    | on-chip    | serial port          |
32| UART         |            |                      |
33+--------------+------------+----------------------+
34| SYSTICK      | on-chip    | system clock         |
35+--------------+------------+----------------------+
36
37The kernel currently does not support other hardware features on this platform.
38
39Devices
40========
41System Clock
42------------
43
44This board configuration uses a system clock frequency of 12 MHz.
45
46Serial Port
47-----------
48
49This board configuration uses a single serial communication channel with the
50CPU's UART0.
51
52If SLIP networking is enabled (see below), an additional serial port will be
53used for it.
54
55Known Problems or Limitations
56==============================
57
58The following platform features are unsupported:
59
60* Memory protection through optional MPU.  However, using a XIP kernel
61  effectively provides TEXT/RODATA write protection in ROM.
62* SRAM at addresses 0x1FFF0000-0x1FFFFFFF
63* Writing to the hardware's flash memory
64
65
66Programming and Debugging
67*************************
68
69Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
70emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
71
72.. zephyr-app-commands::
73   :zephyr-app: samples/synchronization
74   :host-os: unix
75   :board: qemu_cortex_m3
76   :goals: run
77
78This will build an image with the synchronization sample app, boot it using
79QEMU, and display the following console output:
80
81.. code-block:: console
82
83        ***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
84        threadA: Hello World from arm!
85        threadB: Hello World from arm!
86        threadA: Hello World from arm!
87        threadB: Hello World from arm!
88        threadA: Hello World from arm!
89        threadB: Hello World from arm!
90        threadA: Hello World from arm!
91        threadB: Hello World from arm!
92        threadA: Hello World from arm!
93        threadB: Hello World from arm!
94
95Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
96
97Debugging
98=========
99
100Refer to the detailed overview about :ref:`application_debugging`.
101
102Networking
103==========
104
105The board supports SLIP networking over an emulated serial port
106(``CONFIG_NET_SLIP_TAP=y``). The detailed setup is described in
107:ref:`networking_with_qemu`.
108
109It is also possible to use the QEMU built-in Ethernet adapter to connect
110to the host system. This is faster than using SLIP and is also the preferred
111way. See :ref:`networking_with_eth_qemu` for details.
112
113References
114**********
115
1161. The Definitive Guide to the ARM Cortex-M3, Second Edition by Joseph Yiu (ISBN
117   978-0-12-382090-7)
1182. ARMv7-M Architecture Technical Reference Manual (ARM DDI 0403D ID021310)
1193. Procedure Call Standard for the ARM Architecture (ARM IHI 0042E, current
120   through ABI release 2.09, 2012/11/30)
1214. Cortex-M3 Revision r2p1 Technical Reference Manual (ARM DDI 0337I ID072410)
1225. Cortex-M3 Devices Generic User Guide (ARM DUI 0052A ID121610)
123