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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77961.h3 * Copyright (c) 2023-2024 EPAM Systems
5 * SPDX-License-Identifier: Apache-2.0
10 #include "pinctrl-rcar-common.h"
13 #define PIN_NONE -1
54 #define PIN_RD_WR RCAR_GP_PIN(1, 24)
58 #define PIN_CLKOUT RCAR_GP_PIN(1, 28)
132 #define PIN_MLB_SIG RCAR_GP_PIN(5, 24)
158 #define PIN_USB0_PWEN RCAR_GP_PIN(6, 24)
162 #define PIN_USB30_PWEN RCAR_GP_PIN(6, 28)
193 #define PIN_QSPI0_IO2 RCAR_NOGP_PIN(24)
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Dpinctrl-r8a77951.h4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
53 #define PIN_RD_WR RCAR_GP_PIN(1, 24)
57 #define PIN_CLKOUT RCAR_GP_PIN(1, 28)
131 #define PIN_MLB_SIG RCAR_GP_PIN(5, 24)
157 #define PIN_USB0_PWEN RCAR_GP_PIN(6, 24)
161 #define PIN_USB30_PWEN RCAR_GP_PIN(6, 28)
192 #define PIN_QSPI0_IO2 RCAR_NOGP_PIN(24)
196 #define PIN_QSPI0_SPCLK RCAR_NOGP_PIN(28)
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Dpinctrl-r8a779f0.h4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
58 #define PIN_SD_WP RCAR_GP_PIN(1, 24)
119 #define PIN_MSPI0CSS0 RCAR_GP_PIN(4, 24)
123 #define PIN_MSPI1SC RCAR_GP_PIN(4, 28)
194 #define PIN_CAN12TX RCAR_GP_PIN(7, 24)
198 #define PIN_CAN14TX RCAR_GP_PIN(7, 28)
224 #define FUNC_RX0 IP0SR0(24, 0)
225 #define FUNC_HRX1 IP0SR0(24, 1)
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/Zephyr-latest/samples/modules/cmsis_dsp/moving_average/
Dsample.yaml7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
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/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_r8a77951.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
14 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
15 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
25 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
26 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
37 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
47 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
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Dpfc_r8a77961.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h>
14 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
15 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
25 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
26 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
37 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
47 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
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Dpfc_r8a779f0.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h>
15 { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
16 { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
26 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
27 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */
46 { RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */
47 { RCAR_GP_PIN(1, 6), 24, 3 }, /* GP1_06 */
57 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */
58 { RCAR_GP_PIN(1, 14), 24, 3 }, /* MMC_SD_D1 */
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/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_wrover_e_n8r8.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 gpio-reserved-ranges = <20 1>, <24 1>, <28 4>;
12 gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram
13 <20 1>, <24 1>, <28 4>; // NC
17 gpio-reserved-ranges = <5 2>; // GPIO37-38 NC
Desp32_d0wd_v3.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 gpio-reserved-ranges = <20 1>, <24 1>, <28 4>; // NC
/Zephyr-latest/dts/bindings/dsa/
Dmicrochip,ksz8794.yaml2 # SPDX-License-Identifier: Apache-2.0
17 0x02: 1) CAT-5E/6 Short Cable with a Link Issue for the KSZ8795 Family
18 0x04: 2) CAT-5E/6 Short Cable with a Link Issue for the KSZ8795 Family
19 mii-lowspeed-drivestrength:
22 Define the Low-Speed Interface Drive Strength for MII and RMMI
23 Supported values 2,4,8,12,16,20,24,28mA
26 - 2
27 - 4
28 - 8
29 - 12
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/Zephyr-latest/soc/intel/apollo_lake/
Dsoc_gpio.h2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
47 #define APL_GPIO_24 24
51 #define APL_GPIO_28 28
81 #define APL_GPIO_68 24
85 #define APL_GPIO_72 28
131 #define APL_GPIO_PMIC_PWRGOOD 24
135 #define APL_GPIO_215 28
165 #define APL_GPIO_100 24
169 #define APL_GPIO_FST_SPI_CLK_FB 28
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/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
84 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
88 #define MCP251XFD_REG_CON_TXBWS_MASK GENMASK(31, 28)
90 #define MCP251XFD_REG_CON_REQOP_MASK GENMASK(26, 24)
121 #define MCP251XFD_REG_NBTCFG_BRP_MASK GENMASK(31, 24)
127 #define MCP251XFD_REG_DBTCFG_BRP_MASK GENMASK(31, 24)
134 #define MCP251XFD_REG_TDC_SID11EN BIT(24)
141 #define MCP251XFD_REG_TDC_TDCO_MIN -64
153 #define MCP251XFD_REG_VEC_RXCODE_MASK GENMASK(30, 24)
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/Zephyr-latest/boards/ti/common/
Dboosterpack_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "ti,boosterpack-header";
10 #gpio-cells = <2>;
11 gpio-map = <2 0 &gpio0 23 0>,
15 <6 0 &gpio0 24 0>,
27 <24 0 &gpio0 26 0>,
29 <26 0 &gpio0 28 0>,
31 <28 0 &gpio0 30 0>,
/Zephyr-latest/drivers/serial/
Duart_rzt2m.h4 * SPDX-License-Identifier: Apache-2.0
43 #define CCR0_MASK_SSE BIT(24)
50 #define CCR1_MASK_NFEN BIT(28)
58 #define CCR2_MASK_MDDR GENMASK(31, 24)
66 #define CCR3_MASK_CKE (BIT(24) | BIT(25))
67 #define CCR3_CKE_ENABLE BIT(24)
81 #define CSR_MASK_ORER BIT(24)
83 #define CSR_MASK_FER BIT(28)
97 #define CFCLR_MASK_ORERC BIT(24)
100 #define CFCLR_MASK_FERC BIT(28)
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/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
18 /* MIO_PIN_xx SLCR register fields (from Xilinx UG585 v1.13, B.28 SLCR) */
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
132 #define MIO24 24
136 #define MIO28 28
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
176 #define MIO_GROUP_SPI0_1_GRP_PINS 28, 29, 33
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/Zephyr-latest/boards/renesas/da1469x_dk_pro/
Dda1469x_dk_pro-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/pinctrl/smartbond-pinctrl.h>
15 bias-pull-up;
23 bias-pull-up;
27 /omit-if-no-ref/ i2c_sleep: i2c_sleep {
31 bias-pull-up;
38 pinmux = <SMARTBOND_PINMUX(I2C2_SDA, 0, 28)>,
40 bias-pull-up;
44 /omit-if-no-ref/ i2c2_sleep: i2c2_sleep {
46 pinmux = <SMARTBOND_PINMUX(GPIO, 0, 28)>,
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/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dnpcx9_reset.h4 * SPDX-License-Identifier: Apache-2.0
41 #define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28)
67 #define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24)
71 #define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28)
92 #define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24)
96 #define NPCX_RESET_MDMA1 (NPCX_RESET_SWRST_CTL4_OFFSET + 24)
100 #define NPCX_RESET_MDMA5 (NPCX_RESET_SWRST_CTL4_OFFSET + 28)
Dnpcx4_reset.h4 * SPDX-License-Identifier: Apache-2.0
41 #define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28)
68 #define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24)
72 #define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28)
96 #define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24)
104 #define NPCX_RESET_MDMA1 (NPCX_RESET_SWRST_CTL4_OFFSET + 24)
108 #define NPCX_RESET_MDMA5 (NPCX_RESET_SWRST_CTL4_OFFSET + 28)
/Zephyr-latest/subsys/net/lib/http/
Dhttp_huffman.c4 * SPDX-License-Identifier: Apache-2.0
196 { 24, 9, { 0b11111111, 0b11111111, 0b11101010, 0b00000000 } },
197 { 24, 142, { 0b11111111, 0b11111111, 0b11101011, 0b00000000 } },
198 { 24, 144, { 0b11111111, 0b11111111, 0b11101100, 0b00000000 } },
199 { 24, 145, { 0b11111111, 0b11111111, 0b11101101, 0b00000000 } },
200 { 24, 148, { 0b11111111, 0b11111111, 0b11101110, 0b00000000 } },
201 { 24, 159, { 0b11111111, 0b11111111, 0b11101111, 0b00000000 } },
202 { 24, 171, { 0b11111111, 0b11111111, 0b11110000, 0b00000000 } },
203 { 24, 206, { 0b11111111, 0b11111111, 0b11110001, 0b00000000 } },
204 { 24, 215, { 0b11111111, 0b11111111, 0b11110010, 0b00000000 } },
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/Zephyr-latest/soc/microchip/mec/common/
Dsoc_pins.h4 * SPDX-License-Identifier: Apache-2.0
39 #define MCHP_GPIO_030 (24U)
43 #define MCHP_GPIO_034 (28U)
73 #define MCHP_GPIO_070 (24U)
77 #define MCHP_GPIO_074 (28U)
107 #define MCHP_GPIO_130 (24U)
111 #define MCHP_GPIO_134 (28U)
141 #define MCHP_GPIO_170 (24U)
145 #define MCHP_GPIO_174 (28U)
175 #define MCHP_GPIO_230 (24U)
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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Drpi-pico-pinctrl-common.h5 * SPDX-License-Identifier: Apache-2.0
24 /* These function are common. SoC-specific functions are defined in their
61 #define SPI1_RX_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_SPI)
65 #define SPI1_RX_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_SPI)
92 #define UART1_TX_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_UART)
96 #define UART0_TX_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_UART)
123 #define I2C0_SDA_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_I2C)
127 #define I2C0_SDA_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_I2C)
154 #define PWM_4A_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PWM)
158 #define PWM_6A_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PWM)
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/Zephyr-latest/dts/bindings/gpio/
Dquicklogic,eos-s3-gpio.yaml3 compatible: "quicklogic,eos-s3-gpio"
5 include: [gpio-controller.yaml, base.yaml]
11 "#gpio-cells":
14 pin-secondary-config:
22 "0 : 6 / 24"
24 "2 : 11 / 28"
30 E.g. configuring GPIO 2 as secondary results in controlling pin 28,
32 "pin-secondary-config = <0x04>;"
34 gpio-cells:
35 - pin
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/Zephyr-latest/tests/net/lib/http_server/hpack/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
16 /* Copy-paste from RFC7541. */
18 { 0x1ff8, 13, }, { 0x7fffd8, 23, }, { 0xfffffe2, 28, }, { 0xfffffe3, 28, },
19 { 0xfffffe4, 28, }, { 0xfffffe5, 28, }, { 0xfffffe6, 28, }, { 0xfffffe7, 28, },
20 { 0xfffffe8, 28, }, { 0xffffea, 24, }, { 0x3ffffffc, 30, }, { 0xfffffe9, 28, },
21 { 0xfffffea, 28, }, { 0x3ffffffd, 30, }, { 0xfffffeb, 28, }, { 0xfffffec, 28, },
22 { 0xfffffed, 28, }, { 0xfffffee, 28, }, { 0xfffffef, 28, }, { 0xffffff0, 28, },
23 { 0xffffff1, 28, }, { 0xffffff2, 28, }, { 0x3ffffffe, 30, }, { 0xffffff3, 28, },
24 { 0xffffff4, 28, }, { 0xffffff5, 28, }, { 0xffffff6, 28, }, { 0xffffff7, 28, },
25 { 0xffffff8, 28, }, { 0xffffff9, 28, }, { 0xffffffa, 28, }, { 0xffffffb, 28, },
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/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dopenisa-intmux.h4 * SPDX-License-Identifier: Apache-2.0
13 #define INTMUX_CH0_IRQ 24
17 #define INTMUX_CH4_IRQ 28
/Zephyr-latest/boards/circuitdojo/feather/
Dcircuitdojo_feather_nrf9160_common-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
33 low-power-enable;
39 psels = <NRF_PSEL(UART_TX, 0, 24)>,
46 psels = <NRF_PSEL(UART_TX, 0, 24)>,
48 low-power-enable;
63 low-power-enable;
76 low-power-enable;
84 <NRF_PSEL(SPIM_MISO, 0, 28)>;
92 <NRF_PSEL(SPIM_MISO, 0, 28)>;
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