Lines Matching +full:24 +full:- +full:28

4  * SPDX-License-Identifier: Apache-2.0
18 /* MIO_PIN_xx SLCR register fields (from Xilinx UG585 v1.13, B.28 SLCR) */
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
132 #define MIO24 24
136 #define MIO28 28
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS     16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS     28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
176 #define MIO_GROUP_SPI0_1_GRP_PINS          28, 29, 33
188 #define MIO_GROUP_SPI1_1_GRP_PINS          22, 23, 24
201 #define MIO_GROUP_SDIO0_1_GRP_PINS         28, 29, 30, 31, 32, 33
204 #define MIO_GROUP_SDIO1_1_GRP_PINS         22, 23, 24, 25, 26, 27
212 					   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
213 					   28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
233 #define MIO_GROUP_CAN1_4_GRP_PINS          24, 25
234 #define MIO_GROUP_CAN1_5_GRP_PINS          28, 29
256 #define MIO_GROUP_UART1_4_GRP_PINS         24, 25
257 #define MIO_GROUP_UART1_5_GRP_PINS         28, 29
278 #define MIO_GROUP_I2C1_3_GRP_PINS          24, 25
279 #define MIO_GROUP_I2C1_4_GRP_PINS          28, 29
290 #define MIO_GROUP_TTC1_1_GRP_PINS          28, 29
321 #define MIO_GROUP_GPIO0_24_GRP_PINS        24
325 #define MIO_GROUP_GPIO0_28_GRP_PINS        28
351 #define MIO_GROUP_USB0_0_GRP_PINS          28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
360 /* Iterate over each pinctrl-n phandle child */
367  *   - Iterate over each pin in group and populate pinctrl_soc_pin_t
369  *   - Iterate over each pin in pins and populate pinctrl_soc_pin_t