Lines Matching +full:24 +full:- +full:28
2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
14 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
15 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
25 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
26 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
37 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
47 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
48 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
58 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
59 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
69 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
70 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
80 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
81 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
91 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
92 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
102 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
103 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
107 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
113 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
114 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
124 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
125 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
135 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
136 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
146 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
147 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
153 { PIN_TDO, 28, 2 }, /* TDO */
154 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
164 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
165 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
175 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
176 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
186 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
187 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
197 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
198 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
208 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
209 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
219 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
220 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
230 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
231 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
234 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
241 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
242 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
252 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
253 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
263 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
264 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
270 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
274 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
275 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
277 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
316 [24] = PIN_AVB_TD1, /* AVB_TD1 */
320 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
350 [24] = RCAR_GP_PIN(1, 12), /* A12 */
354 [28] = RCAR_GP_PIN(1, 16), /* A16 */
360 [0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
365 [5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
384 [24] = RCAR_GP_PIN(0, 14), /* D14 */
388 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
418 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
422 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
452 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
456 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
466 [4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
486 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
490 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
493 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
499 [3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
520 [24] = PIN_NONE,
524 [28] = PIN_NONE,