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/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
48 #define SSCR0_ACS BIT(30)
[all …]
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
47 #define SSCR0_ACS BIT(30)
[all …]
Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
52 #define SSCR0_TIM BIT(23)
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
55 #define SSCR0_EFRDC BIT(27)
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_andes_atciic100.h4 * SPDX-License-Identifier: Apache-2.0
31 ((const struct i2c_atciic100_config * const)(dev)->config)->base
47 #define IEN_CMPL BIT(9)
48 #define IEN_BYTE_RECV BIT(8)
49 #define IEN_BYTE_TRANS BIT(7)
50 #define IEN_START BIT(6)
51 #define IEN_STOP BIT(5)
52 #define IEN_ARB_LOSE BIT(4)
53 #define IEN_ADDR_HIT BIT(3)
54 #define IEN_FIFO_HALF BIT(2)
[all …]
/Zephyr-latest/include/zephyr/math/
Dilog2.h4 * SPDX-License-Identifier: Apache-2.0
25 * This calculates the floor of log2 (integer log2) for 32-bit
31 * nested if-else blocks.
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
[all …]
Dbosch,bmp390.yaml3 # SPDX-License-Identifier: Apache-2.0
7 include: sensor-device.yaml
10 int-gpios:
11 type: phandle-array
17 200 - 200 - 5ms (default; chip reset value)
18 100 - 100 - 10ms
19 50 - 50 - 20ms
20 25 - 25 - 40ms
21 12.5 - 25/2 - 80ms
22 6.25 - 25/4 - 160ms
[all …]
/Zephyr-latest/drivers/spi/
Dspi_pw.h1 /* spi_pw.h - Penwell SPI driver definitions */
6 * SPDX-License-Identifier: Apache-2.0
41 #define PW_SPI_CTRLR0_SSE_BIT BIT(7)
42 #define PW_SPI_CTRLR0_EDSS_BIT BIT(20)
43 #define PW_SPI_CTRLR0_RIM_BIT BIT(22)
44 #define PW_SPI_CTRLR0_TIM_BIT BIT(23)
45 #define PW_SPI_CTRLR0_MOD_BIT BIT(31)
71 #define PW_SPI_CTRL1_RIE_BIT BIT(0)
72 #define PW_SPI_CTRL1_TIE_BIT BIT(1)
73 #define PW_SPI_CTRL1_LBM_BIT BIT(2)
[all …]
/Zephyr-latest/soc/neorv32/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
21 #define NEORV32_SYSINFO_CPU_ZICSR BIT(0)
22 #define NEORV32_SYSINFO_CPU_ZIFENCEI BIT(1)
23 #define NEORV32_SYSINFO_CPU_ZMMUL BIT(2)
24 #define NEORV32_SYSINFO_CPU_ZBB BIT(3)
25 #define NEORV32_SYSINFO_CPU_ZFINX BIT(5)
26 #define NEORV32_SYSINFO_CPU_ZXSCNT BIT(6)
27 #define NEORV32_SYSINFO_CPU_ZXNOCNT BIT(7)
28 #define NEORV32_SYSINFO_CPU_PMP BIT(8)
29 #define NEORV32_SYSINFO_CPU_HPM BIT(9)
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dilm.c4 * SPDX-License-Identifier: Apache-2.0
20 * IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
32 * address range non-cacheable (which is appropriate because Flash has high latency but RAM is
42 BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must be a power of two");
49 #define SCARH_ENABLE BIT(3)
50 #define SCARH_ADDR_BIT19 BIT(7)
53 * SCAR registers contain 20-bit addresses in three registers, with one set
61 /* Bits 16..18 and 19 of address, plus the enable bit for the entire SCAR; SCARnH */
76 return ((uintptr_t)p & (ILM_BLOCK_SIZE - 1)) == 0; in is_block_aligned()
83 return -EFAULT; /* Not in RAM */ in it8xxx2_configure_ilm_block()
[all …]
/Zephyr-latest/drivers/mdio/
Dmdio_adin2111.c4 * SPDX-License-Identifier: Apache-2.0
30 #define ADIN211_MDIOACC_MDIO_TRDONE BIT(31)
39 const struct mdio_adin2111_config *const cfg = dev->config; in mdio_adin2111_wait_ready()
44 ret = eth_adin2111_reg_read(cfg->adin, reg, out); in mdio_adin2111_wait_ready()
49 ret = -ETIMEDOUT; in mdio_adin2111_wait_ready()
62 const struct mdio_adin2111_config *const cfg = dev->config; in mdio_adin2111_read_c45()
68 cmd = (prtad & 0x1FU) << 21; in mdio_adin2111_read_c45()
72 ret = eth_adin2111_reg_write(cfg->adin, ADIN2111_MDIOACC0, cmd); in mdio_adin2111_read_c45()
80 ret = eth_adin2111_reg_write(cfg->adin, ADIN2111_MDIOACC1, cmd); in mdio_adin2111_read_c45()
91 ret = eth_adin2111_reg_read(cfg->adin, ADIN2111_MDIOACC1, &cmd); in mdio_adin2111_read_c45()
[all …]
/Zephyr-latest/drivers/serial/
Duart_rzt2m.h4 * SPDX-License-Identifier: Apache-2.0
36 #define CCR0_MASK_RE BIT(0)
37 #define CCR0_MASK_TE BIT(4)
38 #define CCR0_MASK_DCME BIT(9)
39 #define CCR0_MASK_IDSEL BIT(10)
40 #define CCR0_MASK_RIE BIT(16)
41 #define CCR0_MASK_TIE BIT(20)
42 #define CCR0_MASK_TEIE BIT(21)
43 #define CCR0_MASK_SSE BIT(24)
45 #define CCR1_MASK_CTSE BIT(0)
[all …]
/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
84 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
89 #define MCP251XFD_REG_CON_ABAT BIT(27)
99 #define MCP251XFD_REG_CON_OPMOD_MASK GENMASK(23, 21)
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
101 #define MCP251XFD_REG_CON_STEF BIT(19)
102 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
103 #define MCP251XFD_REG_CON_ESIGM BIT(17)
104 #define MCP251XFD_REG_CON_RTXAT BIT(16)
[all …]
Dcan_sja1000_priv.h4 * SPDX-License-Identifier: Apache-2.0
33 #define CAN_SJA1000_AMR1 (21U)
44 #define CAN_SJA1000_EFF_DATA (21U)
51 #define CAN_SJA1000_MOD_RM BIT(0)
52 #define CAN_SJA1000_MOD_LOM BIT(1)
53 #define CAN_SJA1000_MOD_STM BIT(2)
54 #define CAN_SJA1000_MOD_AFM BIT(3)
55 #define CAN_SJA1000_MOD_SM BIT(4)
58 #define CAN_SJA1000_CMR_TR BIT(0)
59 #define CAN_SJA1000_CMR_AT BIT(1)
[all …]
Dcan_tcan4x5x.c4 * SPDX-License-Identifier: Apache-2.0
21 * The register definitions correspond to those found in the TI TCAN4550-Q1 datasheet, revision D
39 #define CAN_TCAN4X5X_STATUS_INTERNAL_READ_ERROR BIT(29)
40 #define CAN_TCAN4X5X_STATUS_INTERNAL_WRITE_ERROR BIT(28)
41 #define CAN_TCAN4X5X_STATUS_INTERNAL_ERROR_LOG_WRITE BIT(27)
42 #define CAN_TCAN4X5X_STATUS_READ_FIFO_UNDERFLOW BIT(26)
43 #define CAN_TCAN4X5X_STATUS_READ_FIFO_EMPTY BIT(25)
44 #define CAN_TCAN4X5X_STATUS_WRITE_FIFO_OVERFLOW BIT(24)
45 #define CAN_TCAN4X5X_STATUS_SPI_END_ERROR BIT(21)
46 #define CAN_TCAN4X5X_STATUS_INVALID_COMMAND BIT(20)
[all …]
/Zephyr-latest/drivers/dma/
Ddma_dw_common.h4 * SPDX-License-Identifier: Apache-2.0
18 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
21 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
84 #define DW_CHAN_WRITE_EN_ALL MASK(2 * DW_MAX_CHAN - 1, DW_MAX_CHAN)
85 #define DW_CHAN_WRITE_EN(chan) BIT((chan) + DW_MAX_CHAN)
86 #define DW_CHAN_ALL MASK(DW_MAX_CHAN - 1, 0)
87 #define DW_CHAN(chan) BIT(chan)
94 #define DW_CFGL_RELOAD_DST BIT(31)
95 #define DW_CFGL_RELOAD_SRC BIT(30)
96 #define DW_CFGL_DRAIN BIT(10) /* For Intel GPDMA variant only */
[all …]
/Zephyr-latest/soc/cdns/sample_controller32/include/
D_soc_inthandlers.h4 * SPDX-License-Identifier: Apache-2.0
14 * order (low bits first) and will return a mask of that bit that can
19 #include <xtensa/config/core-isa.h>
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/renesas/rzt2m/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
16 #define CNTCR_EN BIT(0)
17 #define CNTCR_HDBG BIT(1)
20 #define PRCRS_CLK BIT(0)
21 #define PRCRS_LPC_RESET BIT(1)
22 #define PRCRS_GPIO BIT(2)
23 #define PRCRS_SYS_CTRL BIT(3)
25 /* Non-safety area protect register */
26 #define PRCRN_PRC0 BIT(0)
27 #define PRCRN_PRC1 BIT(1)
[all …]
/Zephyr-latest/drivers/usb/common/
Dusb_dwc2_hw.h5 * SPDX-License-Identifier: Apache-2.0
123 * used to get/set a bitfield consisting of only one bit.
158 #define USB_DWC2_GAHBCFG_INVDESCENDIANESS BIT(USB_DWC2_GAHBCFG_INVDESCENDIANESS_POS)
160 #define USB_DWC2_GAHBCFG_AHBSINGLE BIT(USB_DWC2_GAHBCFG_AHBSINGLE_POS)
162 #define USB_DWC2_GAHBCFG_NOTIALLDMAWRIT BIT(USB_DWC2_GAHBCFG_NOTIALLDMAWRIT_POS)
163 #define USB_DWC2_GAHBCFG_REMMEMSUPP_POS 21UL
164 #define USB_DWC2_GAHBCFG_REMMEMSUPP BIT(USB_DWC2_GAHBCFG_REMMEMSUPP_POS)
166 #define USB_DWC2_GAHBCFG_PTXFEMPLVL BIT(USB_DWC2_GAHBCFG_PTXFEMPLVL_POS)
168 #define USB_DWC2_GAHBCFG_NPTXFEMPLVL BIT(USB_DWC2_GAHBCFG_NPTXFEMPLVL_POS)
170 #define USB_DWC2_GAHBCFG_DMAEN BIT(USB_DWC2_GAHBCFG_DMAEN_POS)
[all …]
/Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/
D_soc_inthandlers.h4 * SPDX-License-Identifier: Apache-2.0
13 * order (low bits first) and will return a mask of that bit that can
18 #include <xtensa/config/core-isa.h>
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/espressif/common/include/
D_soc_inthandlers.h4 * SPDX-License-Identifier: Apache-2.0
14 * order (low bits first) and will return a mask of that bit that can
19 #include <xtensa/config/core-isa.h>
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
19 #define MIO_PIN_DISABLE_RCVR_MASK BIT(13)
22 #define MIO_PIN_PULLUP_MASK BIT(12)
28 #define MIO_PIN_SPEED_MASK BIT(8)
37 #define MIO_PIN_L1_SEL_MASK BIT(2)
40 #define MIO_PIN_L0_SEL_MASK BIT(1)
43 #define MIO_PIN_TRI_ENABLE_MASK BIT(0)
89 #define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
99 #define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
129 #define MIO21 21
[all …]
/Zephyr-latest/soc/gd/gd32/gd32vf103/
Dnuclei_csr.h5 * SPDX-License-Identifier: Apache-2.0
13 * Use arch/riscv/csr.h for RISC-V standard CSR and definitions.
31 #define MCOUNTINHIBIT_IR BIT(2U)
32 #define MCOUNTINHIBIT_CY BIT(0U)
34 #define MILM_CTL_ILM_BPA (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
35 #define MILM_CTL_ILM_RWECC BIT(3U)
36 #define MILM_CTL_ILM_ECC_EXCP_EN BIT(2U)
37 #define MILM_CTL_ILM_ECC_EN BIT(1U)
38 #define MILM_CTL_ILM_EN BIT(0U)
40 #define MDLM_CTL_DLM_BPA (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
[all …]

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