Lines Matching +full:21 +full:- +full:bit
4 * SPDX-License-Identifier: Apache-2.0
18 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
21 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
84 #define DW_CHAN_WRITE_EN_ALL MASK(2 * DW_MAX_CHAN - 1, DW_MAX_CHAN)
85 #define DW_CHAN_WRITE_EN(chan) BIT((chan) + DW_MAX_CHAN)
86 #define DW_CHAN_ALL MASK(DW_MAX_CHAN - 1, 0)
87 #define DW_CHAN(chan) BIT(chan)
94 #define DW_CFGL_RELOAD_DST BIT(31)
95 #define DW_CFGL_RELOAD_SRC BIT(30)
96 #define DW_CFGL_DRAIN BIT(10) /* For Intel GPDMA variant only */
97 #define DW_CFGL_SRC_SW_HS BIT(10) /* For Synopsys variant only */
98 #define DW_CFGL_DST_SW_HS BIT(11) /* For Synopsys variant only */
99 #define DW_CFGL_FIFO_EMPTY BIT(9)
100 #define DW_CFGL_SUSPEND BIT(8)
101 #define DW_CFGL_CTL_HI_UPD_EN BIT(5)
114 #define DW_CTLL_RELOAD_DST BIT(31)
115 #define DW_CTLL_RELOAD_SRC BIT(30)
116 #define DW_CTLL_LLP_S_EN BIT(28)
117 #define DW_CTLL_LLP_D_EN BIT(27)
120 #define DW_CTLL_FC_P2P SET_BITS(21, 20, 3)
121 #define DW_CTLL_FC_P2M SET_BITS(21, 20, 2)
122 #define DW_CTLL_FC_M2P SET_BITS(21, 20, 1)
123 #define DW_CTLL_FC_M2M SET_BITS(21, 20, 0)
124 #define DW_CTLL_D_SCAT_EN BIT(18)
125 #define DW_CTLL_S_GATH_EN BIT(17)
136 #define DW_CTLL_INT_EN BIT(0)
154 #define DW_FIFO_UPD BIT(26)
173 (((dir) == MEMORY_TO_PERIPHERAL) ? ((lli)->sar) : ((lli)->dar))