Lines Matching +full:21 +full:- +full:bit
4 * SPDX-License-Identifier: Apache-2.0
21 * The register definitions correspond to those found in the TI TCAN4550-Q1 datasheet, revision D
39 #define CAN_TCAN4X5X_STATUS_INTERNAL_READ_ERROR BIT(29)
40 #define CAN_TCAN4X5X_STATUS_INTERNAL_WRITE_ERROR BIT(28)
41 #define CAN_TCAN4X5X_STATUS_INTERNAL_ERROR_LOG_WRITE BIT(27)
42 #define CAN_TCAN4X5X_STATUS_READ_FIFO_UNDERFLOW BIT(26)
43 #define CAN_TCAN4X5X_STATUS_READ_FIFO_EMPTY BIT(25)
44 #define CAN_TCAN4X5X_STATUS_WRITE_FIFO_OVERFLOW BIT(24)
45 #define CAN_TCAN4X5X_STATUS_SPI_END_ERROR BIT(21)
46 #define CAN_TCAN4X5X_STATUS_INVALID_COMMAND BIT(20)
47 #define CAN_TCAN4X5X_STATUS_WRITE_OVERFLOW BIT(19)
48 #define CAN_TCAN4X5X_STATUS_WRITE_UNDERFLOW BIT(18)
49 #define CAN_TCAN4X5X_STATUS_READ_OVERFLOW BIT(17)
50 #define CAN_TCAN4X5X_STATUS_READ_UNDERFLOW BIT(16)
51 #define CAN_TCAN4X5X_STATUS_WRITE_FIFO_AVAILABLE BIT(5)
52 #define CAN_TCAN4X5X_STATUS_READ_FIFO_AVAILABLE BIT(4)
53 #define CAN_TCAN4X5X_STATUS_INTERNAL_ACCESS_ACTIVE BIT(3)
54 #define CAN_TCAN4X5X_STATUS_INTERNAL_ERROR_INTERRUPT BIT(2)
55 #define CAN_TCAN4X5X_STATUS_SPI_ERROR_INTERRUPT BIT(1)
56 #define CAN_TCAN4X5X_STATUS_INTERRUPT BIT(0)
69 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_INTERNAL_READ_ERROR BIT(29)
70 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_INTERNAL_WRITE_ERROR BIT(28)
71 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_INTERNAL_ERROR_LOG_WRITE BIT(27)
72 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_READ_FIFO_UNDERFLOW BIT(26)
73 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_READ_FIFO_EMPTY BIT(25)
74 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_WRITE_FIFO_OVERFLOW BIT(24)
75 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_SPI_END_ERROR BIT(21)
76 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_INVALID_COMMAND BIT(20)
77 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_WRITE_OVERFLOW BIT(19)
78 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_WRITE_UNDERFLOW BIT(18)
79 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_READ_OVERFLOW BIT(17)
80 #define CAN_TCAN4X5X_SPI_ERROR_STATUS_MASK_READ_UNDERFLOW BIT(16)
86 #define CAN_TCAN4X5X_MODE_CONFIG_CLK_REF BIT(27)
88 #define CAN_TCAN4X5X_MODE_CONFIG_TEST_MODE_EN BIT(21)
89 #define CAN_TCAN4X5X_MODE_CONFIG_NWKRQ_VOLTAGE BIT(19)
90 #define CAN_TCAN4X5X_MODE_CONFIG_WD_BIT_SET BIT(18)
93 #define CAN_TCAN4X5X_MODE_CONFIG_FAIL_SAFE_EN BIT(13)
95 #define CAN_TCAN4X5X_MODE_CONFIG_INH_DIS BIT(9)
96 #define CAN_TCAN4X5X_MODE_CONFIG_NWKRQ_CONFIG BIT(8)
98 #define CAN_TCAN4X5X_MODE_CONFIG_WD_EN BIT(3)
99 #define CAN_TCAN4X5X_MODE_CONFIG_DEVICE_RESET BIT(2)
100 #define CAN_TCAN4X5X_MODE_CONFIG_SWE_DIS BIT(1)
101 #define CAN_TCAN4X5X_MODE_CONFIG_TEST_MODE_CONFIG BIT(0)
114 #define CAN_TCAN4X5X_TEST_ECC_ERR_FORCE_BIT_SEL GENMASK(21, 16)
115 #define CAN_TCAN4X5X_TEST_ECC_ERR_FORCE BIT(12)
116 #define CAN_TCAN4X5X_TEST_ECC_ERR_CHECK BIT(11)
120 #define CAN_TCAN4X5X_IR_CANBUSNOM BIT(31)
121 #define CAN_TCAN4X5X_IR_SMS BIT(23)
122 #define CAN_TCAN4X5X_IR_UVSUP BIT(22)
123 #define CAN_TCAN4X5X_IR_UVIO BIT(21)
124 #define CAN_TCAN4X5X_IR_PWRON BIT(20)
125 #define CAN_TCAN4X5X_IR_TSD BIT(19)
126 #define CAN_TCAN4X5X_IR_WDTO BIT(18)
127 #define CAN_TCAN4X5X_IR_ECCERR BIT(16)
128 #define CAN_TCAN4X5X_IR_CANINT BIT(15)
129 #define CAN_TCAN4X5X_IR_LWU BIT(14)
130 #define CAN_TCAN4X5X_IR_WKERR BIT(13)
131 #define CAN_TCAN4X5X_IR_CANSLNT BIT(10)
132 #define CAN_TCAN4X5X_IR_CANDOM BIT(8)
133 #define CAN_TCAN4X5X_IR_GLOBALERR BIT(7)
134 #define CAN_TCAN4X5X_IR_WKRQ BIT(6)
135 #define CAN_TCAN4X5X_IR_CANERR BIT(5)
136 #define CAN_TCAN4X5X_IR_SPIERR BIT(3)
137 #define CAN_TCAN4X5X_IR_M_CAN_INT BIT(1)
138 #define CAN_TCAN4X5X_IR_VTWD BIT(0)
149 #define CAN_TCAN4X5X_MCAN_IR_ARA BIT(29)
150 #define CAN_TCAN4X5X_MCAN_IR_PED BIT(28)
151 #define CAN_TCAN4X5X_MCAN_IR_PEA BIT(27)
152 #define CAN_TCAN4X5X_MCAN_IR_WDI BIT(26)
153 #define CAN_TCAN4X5X_MCAN_IR_BO BIT(25)
154 #define CAN_TCAN4X5X_MCAN_IR_EW BIT(24)
155 #define CAN_TCAN4X5X_MCAN_IR_EP BIT(23)
156 #define CAN_TCAN4X5X_MCAN_IR_ELO BIT(22)
157 #define CAN_TCAN4X5X_MCAN_IR_BEU BIT(21)
158 #define CAN_TCAN4X5X_MCAN_IR_BEC BIT(20)
159 #define CAN_TCAN4X5X_MCAN_IR_DRX BIT(19)
160 #define CAN_TCAN4X5X_MCAN_IR_TOO BIT(18)
161 #define CAN_TCAN4X5X_MCAN_IR_MRAF BIT(17)
162 #define CAN_TCAN4X5X_MCAN_IR_TSW BIT(16)
163 #define CAN_TCAN4X5X_MCAN_IR_TEFL BIT(15)
164 #define CAN_TCAN4X5X_MCAN_IR_TEFF BIT(14)
165 #define CAN_TCAN4X5X_MCAN_IR_TEFW BIT(13)
166 #define CAN_TCAN4X5X_MCAN_IR_TEFN BIT(12)
167 #define CAN_TCAN4X5X_MCAN_IR_TFE BIT(11)
168 #define CAN_TCAN4X5X_MCAN_IR_TCF BIT(10)
169 #define CAN_TCAN4X5X_MCAN_IR_TC BIT(9)
170 #define CAN_TCAN4X5X_MCAN_IR_HPM BIT(8)
171 #define CAN_TCAN4X5X_MCAN_IR_RF1L BIT(7)
172 #define CAN_TCAN4X5X_MCAN_IR_RF1F BIT(6)
173 #define CAN_TCAN4X5X_MCAN_IR_RF1W BIT(5)
174 #define CAN_TCAN4X5X_MCAN_IR_RF1N BIT(4)
175 #define CAN_TCAN4X5X_MCAN_IR_RF0L BIT(3)
176 #define CAN_TCAN4X5X_MCAN_IR_RF0F BIT(2)
177 #define CAN_TCAN4X5X_MCAN_IR_RF0W BIT(1)
178 #define CAN_TCAN4X5X_MCAN_IR_RF0N BIT(0)
182 #define CAN_TCAN4X5X_IE_UVSUP BIT(22)
183 #define CAN_TCAN4X5X_IE_UVIO BIT(21)
184 #define CAN_TCAN4X5X_IE_TSD BIT(19)
185 #define CAN_TCAN4X5X_IE_ECCERR BIT(16)
186 #define CAN_TCAN4X5X_IE_CANINT BIT(15)
187 #define CAN_TCAN4X5X_IE_LWU BIT(14)
188 #define CAN_TCAN4X5X_IE_CANSLNT BIT(10)
189 #define CAN_TCAN4X5X_IE_CANDOM BIT(8)
241 const struct can_mcan_config *mcan_config = dev->config; in tcan4x5x_read()
242 const struct tcan4x5x_config *tcan_config = mcan_config->custom; in tcan4x5x_read()
271 /* Maximum transfer size is 256 32-bit words */ in tcan4x5x_read()
275 err = spi_transceive_dt(&tcan_config->spi, &tx, &rx); in tcan4x5x_read()
292 const struct can_mcan_config *mcan_config = dev->config; in tcan4x5x_write()
293 const struct tcan4x5x_config *tcan_config = mcan_config->custom; in tcan4x5x_write()
321 /* Maximum transfer size is 256 32-bit words */ in tcan4x5x_write()
329 err = spi_transceive_dt(&tcan_config->spi, &tx, &rx); in tcan4x5x_write()
379 pending = MIN(len - upto, sizeof(buf)); in tcan4x5x_clear_mcan_mram()
395 const struct can_mcan_config *mcan_config = dev->config; in tcan4x5x_get_core_clock()
396 const struct tcan4x5x_config *tcan_config = mcan_config->custom; in tcan4x5x_get_core_clock()
398 *rate = tcan_config->clk_freq; in tcan4x5x_get_core_clock()
408 k_sem_give(&tcan_data->int_sem); in tcan4x5x_int_gpio_callback_handler()
417 struct can_mcan_data *mcan_data = dev->data; in tcan4x5x_int_thread()
418 struct tcan4x5x_data *tcan_data = mcan_data->custom; in tcan4x5x_int_thread()
424 k_sem_take(&tcan_data->int_sem, K_FOREVER); in tcan4x5x_int_thread()
474 const struct can_mcan_config *mcan_config = dev->config; in tcan4x5x_wake()
475 const struct tcan4x5x_config *tcan_config = mcan_config->custom; in tcan4x5x_wake()
480 if (tcan_config->wake_gpio.port != NULL && tcan_config->nwkrq_gpio.port != NULL) { in tcan4x5x_wake()
481 wake_needed = gpio_pin_get_dt(&tcan_config->nwkrq_gpio); in tcan4x5x_wake()
489 if (tcan_config->wake_gpio.port != NULL && wake_needed != 0) { in tcan4x5x_wake()
490 err = gpio_pin_set_dt(&tcan_config->wake_gpio, 1); in tcan4x5x_wake()
498 err = gpio_pin_set_dt(&tcan_config->wake_gpio, 0); in tcan4x5x_wake()
511 const struct can_mcan_config *mcan_config = dev->config; in tcan4x5x_reset()
512 const struct tcan4x5x_config *tcan_config = mcan_config->custom; in tcan4x5x_reset()
521 if (tcan_config->rst_gpio.port != NULL) { in tcan4x5x_reset()
522 err = gpio_pin_set_dt(&tcan_config->rst_gpio, 1); in tcan4x5x_reset()
530 err = gpio_pin_set_dt(&tcan_config->rst_gpio, 0); in tcan4x5x_reset()
554 const struct can_mcan_config *mcan_config = dev->config; in tcan4x5x_init()
555 const struct tcan4x5x_config *tcan_config = mcan_config->custom; in tcan4x5x_init()
556 struct can_mcan_data *mcan_data = dev->data; in tcan4x5x_init()
557 struct tcan4x5x_data *tcan_data = mcan_data->custom; in tcan4x5x_init()
563 k_sem_init(&tcan_data->int_sem, 1, 1); in tcan4x5x_init()
565 if (!spi_is_ready_dt(&tcan_config->spi)) { in tcan4x5x_init()
567 return -ENODEV; in tcan4x5x_init()
571 if (tcan_config->rst_gpio.port != NULL) { in tcan4x5x_init()
572 if (!gpio_is_ready_dt(&tcan_config->rst_gpio)) { in tcan4x5x_init()
574 return -ENODEV; in tcan4x5x_init()
577 err = gpio_pin_configure_dt(&tcan_config->rst_gpio, GPIO_OUTPUT_INACTIVE); in tcan4x5x_init()
580 return -ENODEV; in tcan4x5x_init()
586 if (tcan_config->nwkrq_gpio.port != NULL) { in tcan4x5x_init()
587 if (!gpio_is_ready_dt(&tcan_config->nwkrq_gpio)) { in tcan4x5x_init()
589 return -ENODEV; in tcan4x5x_init()
592 err = gpio_pin_configure_dt(&tcan_config->nwkrq_gpio, GPIO_INPUT); in tcan4x5x_init()
595 return -ENODEV; in tcan4x5x_init()
601 if (tcan_config->wake_gpio.port != NULL) { in tcan4x5x_init()
602 if (!gpio_is_ready_dt(&tcan_config->wake_gpio)) { in tcan4x5x_init()
604 return -ENODEV; in tcan4x5x_init()
607 err = gpio_pin_configure_dt(&tcan_config->wake_gpio, GPIO_OUTPUT_INACTIVE); in tcan4x5x_init()
610 return -ENODEV; in tcan4x5x_init()
615 if (!gpio_is_ready_dt(&tcan_config->int_gpio)) { in tcan4x5x_init()
617 return -ENODEV; in tcan4x5x_init()
620 err = gpio_pin_configure_dt(&tcan_config->int_gpio, GPIO_INPUT); in tcan4x5x_init()
623 return -ENODEV; in tcan4x5x_init()
626 gpio_init_callback(&tcan_data->int_gpio_cb, tcan4x5x_int_gpio_callback_handler, in tcan4x5x_init()
627 BIT(tcan_config->int_gpio.pin)); in tcan4x5x_init()
629 err = gpio_add_callback_dt(&tcan_config->int_gpio, &tcan_data->int_gpio_cb); in tcan4x5x_init()
632 return -ENODEV; in tcan4x5x_init()
636 err = gpio_pin_interrupt_configure_dt(&tcan_config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE); in tcan4x5x_init()
639 return -ENODEV; in tcan4x5x_init()
642 tid = k_thread_create(&tcan_data->int_thread, tcan_data->int_stack, in tcan4x5x_init()
643 K_KERNEL_STACK_SIZEOF(tcan_data->int_stack), in tcan4x5x_init()
651 return -ENODEV; in tcan4x5x_init()
660 return -EIO; in tcan4x5x_init()
676 return -ENODEV; in tcan4x5x_init()
683 if (tcan_config->clk_freq == MHZ(20)) { in tcan4x5x_init()
694 return -ENODEV; in tcan4x5x_init()
703 return -EIO; in tcan4x5x_init()