Lines Matching +full:21 +full:- +full:bit
4 * SPDX-License-Identifier: Apache-2.0
19 #define MIO_PIN_DISABLE_RCVR_MASK BIT(13)
22 #define MIO_PIN_PULLUP_MASK BIT(12)
28 #define MIO_PIN_SPEED_MASK BIT(8)
37 #define MIO_PIN_L1_SEL_MASK BIT(2)
40 #define MIO_PIN_L0_SEL_MASK BIT(1)
43 #define MIO_PIN_TRI_ENABLE_MASK BIT(0)
89 #define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
99 #define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
129 #define MIO21 21
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
172 #define MIO_GROUP_SPI0_0_GRP_PINS 16, 17, 21
200 #define MIO_GROUP_SDIO0_0_GRP_PINS 16, 17, 18, 19, 20, 21
212 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
217 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23
232 #define MIO_GROUP_CAN1_3_GRP_PINS 20, 21
255 #define MIO_GROUP_UART1_3_GRP_PINS 20, 21
277 #define MIO_GROUP_I2C1_2_GRP_PINS 20, 21
318 #define MIO_GROUP_GPIO0_21_GRP_PINS 21
360 /* Iterate over each pinctrl-n phandle child */
367 * - Iterate over each pin in group and populate pinctrl_soc_pin_t
369 * - Iterate over each pin in pins and populate pinctrl_soc_pin_t