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/Zephyr-latest/samples/tfm_integration/tfm_regression_test/
Dsample.yaml8 - nrf5340dk/nrf5340/cpuapp/ns
9 - nrf9160dk/nrf9160/ns
10 - nrf9161dk/nrf9161/ns
11 - v2m_musca_s1/musca_s1/ns
13 - nrf5340dk/nrf5340/cpuapp/ns
30 timeout: 200
33 timeout: 200
39 timeout: 200
/Zephyr-latest/dts/bindings/led_strip/
Dws2812.yaml15 A 0 bit's pulse width is between 200 and 500 ns. A 1 bit's is
16 at least 550 ns, with 700 ns or so typical. Pixel order is GRB.
28 0 bit: 300 ns high and 900 ns low.
29 1 bit: 900 ns high and 300 ns low.
31 There is a +/- 80 ns tolerance for each timing.
/Zephyr-latest/dts/bindings/fpga/
Dlattice,ice40-fpga-base.yaml30 The datasheet specifies a minimum of 200ns, therefore the default is set
/Zephyr-latest/drivers/fpga/
Dfpga_ice40_common.h25 #define FPGA_ICE40_CRESET_DELAY_US_MIN 1 /* 200ns absolute minimum */
Dfpga_ice40_spi.c76 /* Wait a minimum of 200ns */ in fpga_ice40_load()
Dfpga_ice40_bitbang.c176 /* Wait a minimum of 200ns */ in fpga_ice40_load()
/Zephyr-latest/kernel/paging/
Dstatistics.c39 #define NS_TO_CYC(ns) (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000000U * ns) argument
51 NS_TO_CYC(200),
/Zephyr-latest/boards/arm/mps2/doc/
Dmps2_an521.rst49 | mps2/an521/cpu0/ns | For building Non-Secure firmware for CPU0 |
64 ignoring the S/NS alias difference.
67 | Board | CPU | Code (Offset) | SRAM (Offset) | S/NS Alias |
71 | mps2/an521/cpu0/ns | 0 | 512KB (1MB) | 512KB (1MB) | NS |
73 | mps2/an521/cpu1 | 1 | 468KB (3628KB) | 512KB (1.5MB) | NS |
76 The ``mps2/an521/cpu0/ns`` board target is intended to be used with TF-M, with the
95 When using one of the alternative board targets (``mps2/an521/cpu0/ns`` or
106 - Soft Macro Model (SMM) implementation of SSE-200 subsystem
214 | | | from ns space | |
413 for MPS2+ AN521 (CPU0) using ``-DBOARD=mps2/an521/cpu0/ns``.
[all …]
/Zephyr-latest/boards/arm/v2m_musca_s1/doc/
Dindex.rst133 | | | from ns space | |
220 multiplied to drive the Cortex-M33 processors and SSE-200 subsystem. The
221 default is 50MHz but can be increased to 200MHz maximum for the secondary
274 For more details please refer to `Corelink SSE-200 Subsystem`_.
387 The TF-M integration samples can be run using the ``v2m_musca_s1/musca_s1/ns``
393 :board: v2m_musca_s1/musca_s1/ns
426 .. _Corelink SSE-200 Subsystem:
427 https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200
/Zephyr-latest/boards/arm/v2m_musca_b1/doc/
Dindex.rst136 | | | from ns space | |
226 multiplied to drive the Cortex-M33 processors and SSE-200 subsystem. The
280 For more details please refer to `Corelink SSE-200 Subsystem`_.
398 .. _Corelink SSE-200 Subsystem:
399 https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200
/Zephyr-latest/tests/net/ipv6/src/
Dmain.c70 /* ICMPv6 NS frame (74 bytes) */
78 /* ICMPv6 NS header starts here */
93 /* ICMPv6 NS frame (64 bytes) */
101 /* ICMPv6 NS header starts here */
702 * @brief IPv6 send NS extra options
720 "Data receive for invalid NS failed."); in ZTEST()
725 * @brief IPv6 send NS no option
743 "Data receive for invalid NS failed."); in ZTEST()
796 "Timeout while waiting for expected NS"); in ZTEST()
806 /* Second attempt (neighbor valid) should give no NS. */ in ZTEST()
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_tca6424a.c486 /* RESET signal needs to be active for a minimum of 30 ns. */ in tca6424a_init()
494 /* Give the expander at least 200 ns to recover after reset. */ in tca6424a_init()
Dgpio_pcal64xxa.c888 /* RESET signal needs to be active for a minimum of 30 ns. */ in pcal64xxa_apply_initial_state()
897 /* Give the expander at least 200 ns to recover after reset. */ in pcal64xxa_apply_initial_state()
/Zephyr-latest/boards/st/nucleo_l552ze_q/doc/
Dnucleol552ze_q.rst96 - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS
189 | nucleo_l552ze_q/stm32l552xx/ns | For building Non-Secure firmware |
197 $ west build -b nucleo_l552ze_q/stm32l552xx/ns samples/tfm_integration/tfm_ipc/
/Zephyr-latest/boards/st/stm32l562e_dk/doc/
Dindex.rst112 - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS
215 | stm32l562e_dk/stm32l562xx/ns | For building Non-Secure firmware |
223 $ west build -b stm32l562e_dk/stm32l562xx/ns samples/tfm_integration/tfm_ipc/
/Zephyr-latest/doc/services/logging/
Dcs_stm.rst73 It takes less than 100 ns to log a single trace point on NRF54H20 and it is approx. 7 times faster …
214 [00:00:00.292,200] <inf> rad/icmsg: read 0
/Zephyr-latest/doc/hardware/porting/board/
Dboard-terminology.svg3 …ns</b></font></div></div></div></foreignObject><image x="12" y="17.5" width="698" height="59.5" xl…
/Zephyr-latest/subsys/net/l2/ethernet/gptp/
Dgptp_mi.c555 /* Convert ns to ms. */ in gptp_mi_pss_send_state_machine()
840 if (nanosecond_diff < -200) { in gptp_update_local_port_clock()
841 nanosecond_diff = -200; in gptp_update_local_port_clock()
842 } else if (nanosecond_diff > 200) { in gptp_update_local_port_clock()
843 nanosecond_diff = 200; in gptp_update_local_port_clock()
/Zephyr-latest/tests/benchmarks/mbedtls/src/
Dbenchmark.c188 mbedtls_printf("%9lu KiB/s, %9lu ns/byte\n", \
291 unsigned char tmp[200]; in main()
/Zephyr-latest/drivers/i3c/
Di3c_cdns.c473 #define I3C_BUS_TLOW_OD_MIN_NS 200
477 * minimum of the clock rise and fall time plus 3ns
947 /* Calculate the OD_LOW value assuming a desired T_low period of 210ns. */ in cdns_i3c_set_prescalers()
3112 * Should be MIN(t_cf, t_cr) + 3ns
Di3c_npcx.c105 #define I3C_BUS_TLOW_OD_MIN_NS 200 /* T_LOW period in open-drain mode */
2322 LOG_ERR("PPLOW ns out of spec"); in npcx_i3c_get_scl_config()
2340 LOG_ERR("ODBAUD ns out of spec"); in npcx_i3c_get_scl_config()
/Zephyr-latest/doc/releases/
Drelease-notes-3.5.rst527 * Fixed mcux to increase the PTP timestamp accuracy from 20us to 200ns.
/Zephyr-latest/samples/modules/tflite-micro/hello_world/train/
Dtrain_hello_world_model.ipynb843 "Epoch 200/500\n",
1503 …bv/OZg8GUaNqtefbTVKBEmgcFUhd7x2BzOWzaj3Nj079aRVSit6d+ldqU9BRFoeJYIkEksIr69+nS+2frFX2x6cdTCZrTLpkNm…
1575 … reduce until around 200 epochs, at which point it is mostly stable. This means that there's no ne…
2176 "Epoch 200/500\n",