| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | irq_relay.S | 4 * SPDX-License-Identifier: Apache-2.0
10 * @brief IRQ relay vector table and relay handler for Cortex-M0 or
11 * Armv8-M baseline SoCs
13 * In certain ARMv6-M and Armv8-M baseline cores the vector table address can
43 * is the IRQ number times 4 (aka r0 << 2). As know as the r1 stored
44 * the offset of real vector table, thus the (r1 = r1 + r0 << 2) will
53 .word z_main_stack + CONFIG_MAIN_STACK_SIZE
55 .word z_arm_reset
57 .word __vector_relay_handler /* nmi */
58 .word __vector_relay_handler /* hard fault */
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| /Zephyr-latest/dts/bindings/dma/ |
| D | andestech,atcdmac300.yaml | 4 # SPDX-License-Identifier: Apache-2.0
8 include: dma-controller.yaml
17 chain-transfer:
20 "#dma-cells":
23 dma-cells:
24 - channel
25 - slot
26 - channel-config
32 2. slot: DMA peripheral request ID
33 3. channel-config: A 32bit mask specifying the DMA channel configuration
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| D | st,stm32-dma-v2bis.yaml | 2 # SPDX-License-Identifier: Apache-2.0
11 described in the dma.txt file, using a 2-cell specifier for each
13 1. channel: the dma stream from 1 to <dma-requests>
14 2. channel-config: A 32bit mask specifying the DMA channel configuration
17 -bit 5 : DMA cyclic mode config
20 -bit 6-7 : Direction (see dma.h)
25 -bit 9 : Peripheral Increment Address
28 -bit 10 : Memory Increment Address
31 -bit 11-12 : Peripheral data size
33 0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
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| D | gd,gd32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
22 - bit 10: Memory address increase
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| D | st,stm32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 described in the dma.txt file, using a four-cell specifier for each
12 1. channel: the dma stream from 0 to <dma-requests>
13 2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
16 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
17 3. channel-config: A 32bit mask specifying the DMA channel configuration
19 -bit 6-7 : Direction (see dma.h)
24 -bit 9 : Peripheral Increment Address
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| D | st,stm32-bdma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
14 2. slot: bdma request
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
28 -bit 11-12 : Peripheral data size
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| D | st,stm32-dmamux.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
10 for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
11 1. channel: the mux channel from 0 to <dma-channels> - 1
12 2. slot: the request line Multiplexer ID
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
20 -bit 9 : Peripheral Increment Address
23 -bit 10 : Memory Increment Address
26 -bit 11-12 : Peripheral data size
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| D | st,stm32-dma-v2.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 described in the dma.txt file, using a four-cell specifier for each
13 described in the dma.txt file, using a 3-cell specifier for each
15 1. channel: the dma stream from 1 to <dma-requests>
16 2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
17 this value is 0 for Memory-to-memory transfers
18 or a value between <1> .. <dma-generators> (not supported yet)
19 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
20 3. channel-config: A 32bit mask specifying the DMA channel configuration
23 -bit 5 : DMA cyclic mode config
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| D | st,stm32u5-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 DMA clients connected to the STM32 DMA controller must use a three-cell
17 dma-names = "tx", "rx";
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
21 2. slot: DMA periph request ID, which is written in the REQSEL bits of the CxTR2
22 the slot is a value between <0> .. (<dma-requests> - 1).
23 3. channel-config: A 32bit mask specifying the DMA channel configuration
25 -bit 6-7 : Direction (see dma.h)
30 -bit 9 : Peripheral Increment Address
33 -bit 10 : Memory Increment Address
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| /Zephyr-latest/arch/sparc/core/ |
| D | trap_table_svt.S | 4 * SPDX-License-Identifier: Apache-2.0
9 * single-vector trap model, defined in SPARC V8E. The processor
11 * there, two levels of look-up tables are used to find the trap
14 * - Execution time is constant.
15 * - Condition flags are not modified.
16 * - Provides handler with PSR in l0, TBR in l6
17 * - This SVT implementation is less than 400 bytes long. (An MVT
47 srl %l7, 2, %l7
61 .word __sparc_trap_table_svt_00
62 .word __sparc_trap_table_svt_10
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| /Zephyr-latest/include/zephyr/sys/ |
| D | mpsc_pbuf.h | 4 * SPDX-License-Identifier: Apache-2.0
29 * it can be filled by the user (except for the first 2 bits) and when packet
48 /** @brief Flag indicating that buffer size is power of 2.
50 * When buffer size is power of 2 then optimizations are applied.
62 #define MPSC_PBUF_MAX_UTILIZATION BIT(2)
183 /** @brief Put single word packet into a buffer.
185 * Function is optimized for storing a packet which fit into a single word.
186 * Note that 2 bits of that word is used by the buffer.
190 * @param word Packet content consisting of MPSC_PBUF_HDR with valid bit set
194 const union mpsc_pbuf_generic word);
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| D | mpsc_packet.h | 4 * SPDX-License-Identifier: Apache-2.0
24 /** @brief Number of bits in the first word which are used by the buffer. */
25 #define MPSC_PBUF_HDR_BITS 2
27 /** @brief Header that must be added to the first word in each packet.
39 uint32_t data: 32 - MPSC_PBUF_HDR_BITS;
45 uint32_t len: 32 - MPSC_PBUF_HDR_BITS;
|
| /Zephyr-latest/include/zephyr/arch/x86/ia32/ |
| D | thread.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Per-arch thread definition
55 * The following structure defines the set of 'non-volatile' integer registers.
65 * The following registers are considered non-volatile, i.e.
66 * callee-save,
94 unsigned char reg[10]; /* 80 bits: ST[0-7] */
101 * "Intel(r) 64 and IA-32 Architectures Software Developer's Manual
103 * Memory, 32-Bit Format.
107 unsigned short fcw; /* 2 : x87 FPU control word */
108 unsigned short pad1; /* 2 : N/A */
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| /Zephyr-latest/tests/drivers/fuel_gauge/sbs_gauge/src/ |
| D | test_sbs_gauge.c | 5 * SPDX-License-Identifier: Apache-2.0
47 int ret = fuel_gauge_get_props(fixture->dev, prop_types, props, ARRAY_SIZE(props)); in ZTEST_USER_F()
49 zassert_equal(ret, -ENOTSUP, "Getting bad property has a good status."); in ZTEST_USER_F()
60 int ret = fuel_gauge_set_props(fixture->dev, prop_types, props, ARRAY_SIZE(props)); in ZTEST_USER_F()
62 zassert_equal(ret, -ENOTSUP); in ZTEST_USER_F()
74 /* Set Manufacturer's Access to arbitrary word */ in ZTEST_USER_F()
84 /* Set Manufacturer's Access to arbitrary word */ in ZTEST_USER_F()
88 int ret = fuel_gauge_set_props(fixture->dev, prop_types, props, ARRAY_SIZE(props)); in ZTEST_USER_F()
90 zassert_equal(ret, -ENOTSUP); in ZTEST_USER_F()
95 uint16_t word = BIT(15) | BIT(0); in ZTEST_USER_F() local
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| /Zephyr-latest/drivers/led_strip/ |
| D | ws2812_i2s.c | 5 * https://electronut.in/nrf52-i2s-ws2812/
7 * Note: the word "word" refers to a 32-bit integer unless otherwise stated.
10 * This refers to the "I2S word or channel select" clock.
11 * The I2S peripheral sends two 16-bit channel values for each clock period.
12 * A single LED color (8 data bits) will take up one 32-bit word or one LRCK
15 * SPDX-License-Identifier: Apache-2.0
28 #include <zephyr/dt-bindings/led/led.h>
49 /* Serialize an 8-bit color channel value into two 16-bit I2S values (or 1 32-bit
50 * word).
54 uint32_t word = 0; in ws2812_i2s_ser() local
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| /Zephyr-latest/drivers/entropy/ |
| D | entropy_esp32.c | 4 * SPDX-License-Identifier: Apache-2.0
25 /* The PRNG which implements WDEV_RANDOM register gets 2 bits in entropy_esp32_get_u32()
29 * clock cycles after reading previous word. This implementation may actually in entropy_esp32_get_u32()
41 } while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16); in entropy_esp32_get_u32()
54 uint32_t word = entropy_esp32_get_u32(); in entropy_esp32_get_entropy() local
55 uint32_t to_copy = MIN(sizeof(word), len); in entropy_esp32_get_entropy()
57 memcpy(buf_bytes, &word, to_copy); in entropy_esp32_get_entropy()
59 len -= to_copy; in entropy_esp32_get_entropy()
76 return -ENODEV; in entropy_esp32_init()
|
| D | entropy_smartbond.c | 4 * SPDX-License-Identifier: Apache-2.0
37 (CONFIG_ENTROPY_SMARTBOND_ISR_POOL_SIZE - 1)) == 0,
38 "The CONFIG_ENTROPY_SMARTBOND_ISR_POOL_SIZE must be a power of 2!");
41 (CONFIG_ENTROPY_SMARTBOND_THR_POOL_SIZE - 1)) == 0,
42 "The CONFIG_ENTROPY_SMARTBOND_THR_POOL_SIZE must be a power of 2!");
86 CRG_TOP->CLK_AMBA_REG |= CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk; in trng_enable()
87 TRNG->TRNG_CTRL_REG = TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Msk; in trng_enable()
95 CRG_TOP->CLK_AMBA_REG &= ~CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk; in trng_enable()
96 TRNG->TRNG_CTRL_REG = 0; in trng_enable()
106 return TRNG->TRNG_FIFOLVL_REG & FIFO_COUNT_MASK; in trng_available()
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| /Zephyr-latest/samples/drivers/soc_flash_nrf/ |
| D | README.rst | 1 .. zephyr:code-sample:: soc-flash-nrf
3 :relevant-api: flash_interface flash_area_api
24 there is a fixed-partition named ``storage_partition`` defined
27 .. zephyr-app-commands::
28 :zephyr-app: samples/drivers/soc_flash_nrf
36 .. code-block:: console
38 *** Booting Zephyr OS build v2.7.99-17621-g54832687bcbb ***
46 Test 2: Flash write (word array 1)
64 Test 3: Flash erase (2 pages at 0x80000)
67 Test 4: Flash write (word array 2)
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| /Zephyr-latest/dts/bindings/dai/ |
| D | nxp,dai-esai.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dai-esai"
13 dai-index:
21 tx-fifo-watermark:
28 the TX FIFO watermark will be set to DEFAULT_FIFO_DEPTH / 2.
29 rx-fifo-watermark:
36 the RX FIFO watermark will be set to DEFAULT_FIFO_DEPTH / 2.
37 fifo-depth:
48 that the sanity check for tx/rx-fifo-watermark uses DEFAULT_FIFO_DETPH
52 word-width:
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| /Zephyr-latest/arch/arm/core/mpu/ |
| D | nxp_mpu.c | 4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/linker/linker-defs.h>
17 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
28 "`zephyr,memory-region-mpu` was deprecated in favor of `zephyr,memory-attr`");
56 * This internal function performs run-time sanity check for
69 (part->size != 0U) in mpu_partition_is_valid()
71 ((part->size & in mpu_partition_is_valid()
72 (~(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE - 1))) in mpu_partition_is_valid()
73 == part->size) in mpu_partition_is_valid()
75 ((part->start & in mpu_partition_is_valid()
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | i2s.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public APIs for the I2S (Inter-IC Sound) bus drivers.
20 * @brief I2S (Inter-IC Sound) Interface
23 * as common non-standard extensions such as PCM Short/Long Frame Sync,
50 * Word Select (WS) and Serial Data (SD) signals are sampled on the rising edge
55 * -. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-.
56 * SCK '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '
57 * -. .-------------------------------.
58 * WS '-------------------------------' '----
59 * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.
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| D | smbus.h | 4 * SPDX-License-Identifier: Apache-2.0
49 * 0 1 2 3 4 5 6 7 8 9 0
50 * +-+-+-+-+-+-+-+-+-+-+-+
52 * +-+-+-+-+-+-+-+-+-+-+-+
63 * 0 1 2
64 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
65 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
67 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
71 * 0 1 2
72 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
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| /Zephyr-latest/arch/arm/core/mmu/ |
| D | arm_mmu_priv.h | 7 * SPDX-License-Identifier: Apache-2.0
15 * ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
18 * Chapter B3.5.1, fig. B3-4 and B3-5, p. B3-1323 f.
70 /* <-- end MP-/non-MP-specific */
80 #define ARM_MMU_SCTLR_DCACHE_ENABLE_BIT BIT(2)
84 #define ARM_MMU_L2_PT_INDEX(pt) ((uint32_t)pt - (uint32_t)l2_page_tables) /\
89 uint32_t id : 2; /* [00] */
95 uint32_t acc_perms10 : 2;
105 uint32_t id : 2; /* [00] */
114 uint32_t id : 2; /* [00] */
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_stellaris.c | 5 * SPDX-License-Identifier: Apache-2.0
31 value |= mac_addr[2] << 16; in eth_stellaris_assign_mac()
43 struct eth_stellaris_runtime *dev_data = dev->data; in eth_stellaris_flush()
45 if (dev_data->tx_pos != 0) { in eth_stellaris_flush()
46 sys_write32(dev_data->tx_word, REG_MACDATA); in eth_stellaris_flush()
47 dev_data->tx_pos = 0; in eth_stellaris_flush()
48 dev_data->tx_word = 0U; in eth_stellaris_flush()
54 struct eth_stellaris_runtime *dev_data = dev->data; in eth_stellaris_send_byte()
56 dev_data->tx_word |= byte << (dev_data->tx_pos * 8); in eth_stellaris_send_byte()
57 dev_data->tx_pos++; in eth_stellaris_send_byte()
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| /Zephyr-latest/samples/subsys/llext/shell_loader/ |
| D | README.rst | 1 .. zephyr:code-sample:: llext-shell-loader
3 :relevant-api: llext_apis
21 .. zephyr-app-commands::
22 :zephyr-app: samples/subsys/llext/shell_loader
33 All the llext system related commands are available as sub-commands of llext
36 .. code-block:: console
39 llext - Loadable extension commands
61 .. code-block:: console
63 …$ arm-zephyr-eabi-gcc -mlong-calls -mthumb -c -o hello_world.elf tests/subsys/llext/hello_world/he…
64 $ arm-zephyr-eabi-objdump -r -d -x hello_world.elf
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