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4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Per-arch thread definition
55 * The following structure defines the set of 'non-volatile' integer registers.
65 * The following registers are considered non-volatile, i.e.
66 * callee-save,
94 unsigned char reg[10]; /* 80 bits: ST[0-7] */
101 * "Intel(r) 64 and IA-32 Architectures Software Developer's Manual
103 * Memory, 32-Bit Format.
107 unsigned short fcw; /* 2 : x87 FPU control word */
108 unsigned short pad1; /* 2 : N/A */
109 unsigned short fsw; /* 2 : x87 FPU status word */
110 unsigned short pad2; /* 2 : N/A */
111 unsigned short ftw; /* 2 : x87 FPU tag word */
112 unsigned short pad3; /* 2 : N/A */
114 unsigned short cs; /* 2 : x87 FPU instruction pointer selector */
115 unsigned short fop : 11; /* 2 : x87 FPU opcode */
118 unsigned short ds; /* 2 : x87 FPU instr operand ptr selector */
119 unsigned short pad5; /* 2 : N/A */
120 tFpReg fpReg[8]; /* 80 : ST0 -> ST7 */
128 unsigned char reg[10]; /* 80 bits: ST[0-7] or MM[0-7] */
135 unsigned char reg[16]; /* 128 bits: XMM[0-7] */
142 * "Intel 64 and IA-32 Architectures Software Developer's Manual
143 * Volume 2A: Instruction Set Reference, A-M", except for the bytes from offset
153 unsigned short fcw; /* 2 : x87 FPU control word */
154 unsigned short fsw; /* 2 : x87 FPU status word */
155 unsigned char ftw; /* 1 : x87 FPU abridged tag word */
157 unsigned short fop; /* 2 : x87 FPU opcode */
159 unsigned short cs; /* 2 : x87 FPU instruction pointer selector */
160 unsigned short rsrvd1; /* 2 : reserved */
162 unsigned short ds; /* 2 : x87 FPU instr operand ptr selector */
163 unsigned short rsrvd2; /* 2 : reserved */
224 * Un-set for supervisor threads.