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/Zephyr-latest/dts/bindings/clock/
Dst,stm32u5-msi-clock.yaml24 - 2 # range 2 around 16 MHz
33 - 11 # range 11 around 768 KHz
34 - 12 # range 12 around 400 KHz
35 - 13 # range 13 around 200 KHz
36 - 14 # range 14 around 133 KHz
37 - 15 # range 14 around 100 KHz
Dst,stm32-msi-clock.yaml18 - 0 # range 0 around 100 kHz
19 - 1 # range 1 around 200 kHz
20 - 2 # range 2 around 400 kHz
21 - 3 # range 3 around 800 kHz
26 - 8 # range 8 around 16 MHz
/Zephyr-latest/soc/atmel/sam0/common/
DKconfig.saml2x19 bool "Internal 32.768 kHz RC oscillator"
21 Eable the internal 32.768 kHz RC oscillator at startup.
25 bool "External 32.768 kHz clock source"
27 Enable the external 32.768 kHz cloud source at startup.
31 bool "External 32.768 kHz clock is a crystal oscillator"
39 bool "Internal 16 MHz RC oscillator"
41 Enable the internal 16 MHz RC oscillator at startup.
Dsoc_saml2x.c118 /* configure Fout = Fin / 2^(DIV+1) = 31.25 kHz in dfll48m_init()
119 * Fgclk_dfll48m_ref max is 33 kHz in dfll48m_init()
168 | OSCCTRL_DFLLMUL_CSTEP(16) in dfll48m_init()
171 /* use a 32.768 kHz reference ... 48e6 / 32,768 = 1,464.843... */ in dfll48m_init()
174 /* use a 16 MHz -> 31.25 kHz reference... 48e6 / 31,250 = 1,536 in dfll48m_init()
176 * 16 MHz source directly in dfll48m_init()
/Zephyr-latest/boards/st/stm32g081b_eval/
Dstm32g081b_eval.dts164 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
170 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
177 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
181 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
195 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
201 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
208 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
212 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_pcr.h113 #define MCHP_PCR_PROC_CLK_CTRL_6MHZ 16
117 /* PCR Slow Clock Control. Clock divider for 100KHz clock domain */
203 #define MCHP_PCR2_KBC_POS 16
229 #define MCHP_PCR3_LED0_POS 16
265 #define MCHP_PCR4_SPIP_POS 16
276 /* VTR Source 32 KHz Clock (Offset +8Ch) */
284 * Clock monitor 32KHz period counter (Offset +C0h, RO)
285 * Clock monitor 32KHz high counter (Offset +C4h, RO)
286 * Clock monitor 32KHz period counter minimum (Offset +C8h, RW)
287 * Clock monitor 32KHz period counter maximum (Offset +CCh, RW)
[all …]
Dmec172x_vbat.h41 #define MCHP_VBATR_CS_PCS_POS 16
44 /* Enable and start internal 32KHz Silicon Oscillator */
57 /* Select source of peripheral 32KHz clock */
58 #define MCHP_VBATR_CS_PCS_POS 16
/Zephyr-latest/samples/boards/96boards/argonkey/microphone/
DREADME.rst59 - 16KHz sample rate
60 - 16 bits per sample
63 Five seconds of acquisition at a 16KHz sampling rate yields 80,000 16-bit samples.
134 signed 16 bit PCM, Little Endian, mono format @16KHz.
/Zephyr-latest/boards/st/b_g474e_dpow1/
Db_g474e_dpow1.dts106 mul-n = <16>;
158 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
164 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
171 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
175 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
/Zephyr-latest/boards/st/stm32g071b_disco/
Dstm32g071b_disco.dts160 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
166 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
173 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
177 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c22 #define CLK32K_PLL_LOCK_WAIT (16 * 1024)
24 #define CLK32K_XTAL_WAIT (16 * 1024)
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
37 * One 32KHz clock pulse = 1464.84 48 MHz counts.
156 #define XEC_CC_VBATR_CS_XTAL_SE BIT(9) /* crystal XTAL2 used as 32KHz input */
162 /* MEC172x Select source of peripheral 32KHz clock */
163 #define XEC_CC_VBATR_CS_PCS_POS 16
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/Zephyr-latest/samples/shields/x_nucleo_iks02a1/microphone/
DREADME.rst70 - 16KHz sample rate
71 - 16 bits per sample
74 One second of acquisition at a 1 channel 16KHz sampling rate yields 16,000 16-bit samples.
155 signed 16 bit PCM, Little Endian, mono format @16KHz:
/Zephyr-latest/drivers/sensor/st/lis2dh/
DKconfig76 bool "+/-16g"
133 bool "1.6KHz"
137 bool "1.25KHz"
141 bool "5KHz"
/Zephyr-latest/include/zephyr/audio/
Dcodec.h37 AUDIO_PCM_RATE_8K = 8000, /**< 8 kHz sample rate */
38 AUDIO_PCM_RATE_11P025K = 11025, /**< 11.025 kHz sample rate */
39 AUDIO_PCM_RATE_16K = 16000, /**< 16 kHz sample rate */
40 AUDIO_PCM_RATE_22P05K = 22050, /**< 22.05 kHz sample rate */
41 AUDIO_PCM_RATE_24K = 24000, /**< 24 kHz sample rate */
42 AUDIO_PCM_RATE_32K = 32000, /**< 32 kHz sample rate */
43 AUDIO_PCM_RATE_44P1K = 44100, /**< 44.1 kHz sample rate */
44 AUDIO_PCM_RATE_48K = 48000, /**< 48 kHz sample rate */
45 AUDIO_PCM_RATE_96K = 96000, /**< 96 kHz sample rate */
46 AUDIO_PCM_RATE_192K = 192000, /**< 192 kHz sample rate */
[all …]
/Zephyr-latest/drivers/audio/
Dwm8904.h143 kWM8904_SampleRate8kHz = 0x0, /*!< 8 kHz */
144 kWM8904_SampleRate12kHz = 0x1, /*!< 12kHz */
145 kWM8904_SampleRate16kHz = 0x2, /*!< 16kHz */
146 kWM8904_SampleRate24kHz = 0x3, /*!< 24kHz */
147 kWM8904_SampleRate32kHz = 0x4, /*!< 32kHz */
148 kWM8904_SampleRate48kHz = 0x5, /*!< 48kHz */
149 kWM8904_SampleRate11025Hz = 0x6, /*!< 11.025kHz */
150 kWM8904_SampleRate22050Hz = 0x7, /*!< 22.05kHz */
151 kWM8904_SampleRate44100Hz = 0x8 /*!< 44.1kHz */
/Zephyr-latest/soc/nxp/kinetis/
DKconfig77 resulting frequency must be in the range 31.25 kHz to 4 MHz.
85 FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625
86 kHz.
94 Include the 16-byte flash configuration field that stores default
/Zephyr-latest/boards/dragino/lsn50/doc/
Dindex.rst35 - 32 kHz crystal oscillator for RTC (LSE)
36 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
37 - Internal low-power 37 kHz RC ( |plusminus| 5%)
38 - Internal multispeed low-power 65 kHz to 4.2 MHz RC
43 - 2x 16-bit with up to 4 channels
44 - 2x 16-bit with up to 2 channels
45 - 1x 16-bit ultra-low-power timer
48 - 2x 16-bit basic for DAC
/Zephyr-latest/boards/dragino/nbsn95/doc/
Dindex.rst34 - 32 kHz crystal oscillator for RTC (LSE)
35 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
36 - Internal low-power 37 kHz RC ( |plusminus| 5%)
37 - Internal multispeed low-power 65 kHz to 4.2 MHz RC
42 - 2x 16-bit with up to 4 channels
43 - 2x 16-bit with up to 2 channels
44 - 1x 16-bit ultra-low-power timer
47 - 2x 16-bit basic for DAC
/Zephyr-latest/boards/alientek/pandora_stm32l475/doc/
Dindex.rst45 - 32 kHz crystal oscillator for RTC (LSE)
46 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
47 - Internal low-power 32 kHz RC ( |plusminus| 5%)
48 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
52 - 16x timers:
53 - 2x 16-bit advanced motor-control
54 - 2x 32-bit and 7x 16-bit general purpose
55 - 2x 16-bit basic
56 - 2x low-power 16-bit timers (available in Stop mode)
67 - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS
[all …]
/Zephyr-latest/soc/ite/ec/common/
Dvector.S78 * The content of 16-bytes must be the following and at offset 0x80 of binary.
80 * 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th
89 * bit4: 1b = 32.768KHz is from the internal clock generator.
96 .balign 16
107 .byte 0xA4 /* use external 32.768 kHz oscillator */
/Zephyr-latest/drivers/ieee802154/
DKconfig.mcr20a36 bool "16 MHz"
48 bool "250 kHz"
/Zephyr-latest/dts/bindings/sensor/
Dti,fdc2x1x.yaml45 Reference frequency of the used clock source in KHz.
46 The internal clock oscillates at around 43360 KHz (43.36 MHz)
48 Recommended external clock source frequency is 40000 KHz (40 MHz).
168 3 = Gain = 16 | Effective Resolution 16 bits | 6.25% full scale
/Zephyr-latest/boards/st/stm32wb5mmg/doc/
Dstm32wb5mmg.rst27 - Fully integrated BOM, including 32 MHz radio and 32 kHz RTC crystals
79 - 32 kHz crystal oscillator for RTC (LSE)
80 - Internal low-power 32 kHz (±5%) RC (LSI1)
81 - Internal low-power 32 kHz (stability
83 - Internal multispeed 100 kHz to 48 MHz
86 - High speed internal 16 MHz factory
99 - 1x 16-bit, four channels advanced timer
100 - 2x 16-bit, two channels timers
102 - 2x 16-bit ultra-low-power timers
127 - 12-bit ADC 4.26 Msps, up to 16-bit with
/Zephyr-latest/boards/st/nucleo_l412rb_p/doc/
Dindex.rst13 - 32.768 kHz crystal oscillator
50 - 16 nA Shutdown mode (4 wakeup pins)
75 - 32 kHz crystal oscillator for RTC (LSE)
76 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
77 - Internal low-power 32 kHz RC ( |plusminus| 5%)
78 …- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than |plusminus| 0…
87 - 1x 16-bit advanced motor-control
88 - 1x 32-bit and 2x 16-bit general purpose
89 - 1x 16-bit basic
90 - 2x low-power 16-bit timers (available in Stop mode)
[all …]
/Zephyr-latest/boards/st/stm32l476g_disco/doc/
Dindex.rst53 - 32 kHz crystal oscillator for RTC (LSE)
54 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
55 - Internal low-power 32 kHz RC ( |plusminus| 5%)
56 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
62 - 16x timers:
63 - 2x 16-bit advanced motor-control
64 - 2x 32-bit and 5x 16-bit general purpose
65 - 2x 16-bit basic
66 - 2x low-power 16-bit timers (available in Stop mode)
77 - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS
[all …]

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