1/*
2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3 * Jyunlin Chen <jyunlin.chen@ite.com.tw>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include "chip_chipregs.h"
9#include <zephyr/toolchain.h>
10
11/* exports */
12GTEXT(__start)
13
14/* imports */
15GTEXT(__initialize)
16GTEXT(_isr_wrapper)
17
18SECTION_FUNC(vectors, __start)
19#ifdef CONFIG_RISCV_GP
20	.option push
21	.option norelax
22	/* Configure the GP register */
23	la gp, __global_pointer$
24	.option pop
25#endif
26
27	.option norvc;
28
29#ifdef CONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE
30	/* Enable JTAG debug interface */
31	la t0, IT8XXX2_GCTRL_PMER3
32	lb t1, 0(t0)
33	ori t1, t1, IT8XXX2_GCTRL_JTAG
34	sb t1, 0(t0)
35
36	la t0, IT8XXX2_JTAG_PINS_BASE
37	li t1, 0
38	/* Configure GPIOA0 as TCK function */
39	sb t1, 0(t0)
40	/* Configure GPIOA1 as TDI function */
41	sb t1, 1(t0)
42	/* Configure GPIOA4 as TDO function */
43	sb t1, 4(t0)
44	/* Configure GPIOA5 as TMS function */
45	sb t1, 5(t0)
46	/* Configure GPIOA6 as TRST function */
47	sb t1, 6(t0)
48
49	/* I/O voltage is 3.3V */
50	la t0, IT8XXX2_JTAG_VOLT_SET
51	sb t1, 0(t0)
52#endif
53
54	/*
55	 * Set mtvec (Machine Trap-Vector Base-Address Register)
56	 * to _isr_wrapper.
57	 */
58	la t0, _isr_wrapper
59	csrw mtvec, t0
60	csrwi mie, 0
61#if (CONFIG_SOC_IT8XXX2_FLASH_SIZE_BYTES == 0x100000)
62	/*
63	 * bit[3-0]@EIDSR=8: instruction local memory size is 1M byte
64	 * This operation must be done before accessing memory.
65	 */
66	la t0, IT8XXX2_GCTRL_EIDSR
67	lb t1, 0(t0)
68	andi t1, t1, 0xf0
69	ori  t1, t1, 0x8
70	sb t1, 0(t0)
71#endif
72	/* Jump to __initialize */
73	tail __initialize
74
75/*
76 * eflash signature used to enable specific function after power-on reset.
77 * (HW mechanism)
78 * The content of 16-bytes must be the following and at offset 0x80 of binary.
79 * ----------------------------------------------------------------------------
80 * 1st 2nd 3rd 4th 5th 6th 7th    8th    9th 10th 11th 12th 13th 14th 15th 16th
81 * ----------------------------------------------------------------------------
82 * A5h A5h A5h A5h A5h A5h [host] [flag] 85h  12h  5Ah  5Ah  AAh  AAh  55h  55h
83 * ----------------------------------------------------------------------------
84 * [host]: A4h = enable eSPI, A5h = enable LPC
85 * [flag]:
86 * bit7: it must be 1b.
87 * bit6: it must be 0b.
88 * bit5: it must be 1b.
89 * bit4: 1b = 32.768KHz is from the internal clock generator.
90 * bit3: it must be 0b.
91 * bit2: it must be 1b.
92 * bit1: it must be 0b.
93 * bit0: it must be 0b.
94 */
95.org 0x80
96.balign 16
97.global eflash_sig
98eflash_sig:
99.byte 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5
100#ifdef CONFIG_ESPI
101.byte 0xA4 /* enable eSPI */
102#else
103.byte 0xA5 /* enable LPC */
104#endif
105/* flag of signature */
106#ifdef CONFIG_SOC_IT8XXX2_EXT_32K
107.byte 0xA4 /* use external 32.768 kHz oscillator */
108#else
109.byte 0xB4 /* enable internal clock generator */
110#endif
111.byte 0x85, 0x12, 0x5A, 0x5A, 0xAA, 0xAA, 0x55, 0x55
112