| /Zephyr-latest/subsys/bluetooth/audio/ |
| D | csip_crypto.h | 13 #define BT_CSIP_CRYPTO_KEY_SIZE 16
14 #define BT_CSIP_CRYPTO_SALT_SIZE 16
25 * @param sirk 16 byte LS byte first SIRK
37 * with a key K. The value of K depends on the transport on which the pairing
40 * If the pairing was performed on BR/EDR, K is equal to the Link Key shared by
42 * K = Link Key.
44 * If the pairing was performed on LE, the 64 LSBs of K correspond to the 64
47 * Part H, Section 2.1 in [2]), and the 64 MSBs of K correspond to the 64 MSBs
49 * K = LTK_64-127 || IRK_0-63
51 * @param k 16-byte key.
[all …]
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| D | csip_crypto.c | 63 * sih(k, r) = e(k, r') mod 2^24 in bt_csip_sih()
88 * @param salt A 16-byte salt.
91 * @param out A 16-byte output buffer.
96 const uint8_t *p, size_t p_size, uint8_t out[16]) in k1() argument
101 uint8_t t[16]; in k1()
124 LOG_DBG("BE: out %s", bt_hex(out, 16)); in k1()
134 * @param out 16-byte output buffer.
140 uint8_t zero[16]; in s1()
153 LOG_DBG("BE: out %s", bt_hex(out, 16)); in s1()
158 int bt_csip_sef(const uint8_t k[BT_CSIP_CRYPTO_KEY_SIZE], const uint8_t sirk[BT_CSIP_SIRK_SIZE], in bt_csip_sef()
[all …]
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| /Zephyr-latest/lib/hash/ |
| D | hash_func32_murmur3.c | 10 static inline uint32_t murmur_32_scramble(uint32_t k) in murmur_32_scramble() argument
12 k *= 0xcc9e2d51; in murmur_32_scramble()
13 k = (k << 15) | (k >> 17); in murmur_32_scramble()
14 k *= 0x1b873593; in murmur_32_scramble()
16 return k; in murmur_32_scramble()
21 uint32_t k; in sys_hash32_murmur3() local
27 k = *(const uint32_t *)str; in sys_hash32_murmur3()
28 h ^= murmur_32_scramble(k); in sys_hash32_murmur3()
33 for (k = 0; n != 0; --n, ++str) { in sys_hash32_murmur3()
34 k <<= 8; in sys_hash32_murmur3()
[all …]
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| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/ |
| D | Kconfig.soc | 21 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins.
28 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins,
36 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins.
43 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins,
51 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins,
52 up to 16 transceivers.
59 350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins,
60 up to 16 transceivers.
67 444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins,
68 up to 16 transceivers.
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_lpc55S0x_common.dtsi | 38 * LPC5502: RAMX: 16K, SRAM0: 32K
39 * LPC55x04: RAMX: 16K, SRAM0: 32K, SRAM1: 16K
40 * LPC55x06: RAMX: 16K, SRAM0: 32K, SRAM1: 16K, SRAM2: 16K, SRAM3: 16k
44 reg = <0x04000000 DT_SIZE_K(16)>;
52 reg = <0x20008000 DT_SIZE_K(16)>;
56 reg = <0x2000C000 DT_SIZE_K(16)>;
60 reg = <0x20010000 DT_SIZE_K(16)>;
175 interrupts = <16 0>;
204 resets = <&reset NXP_SYSCON_RESET(1, 16)>;
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| D | nxp_lpc54xxx.dtsi | 53 * (note: reference manual says "up to <n>K")
56 * LPC540xx: RAMX: 192K, SRAM0: 64K, SRAM1: 32K, SRAM2: 32K, SRAM3: 32K, USBRAM: 8K
57 * LPC5410x: RAMX: ----, SRAM0: 64K, SRAM1: 32K, USBRAM: 8K @ 0x03400000
58 * LPC5411x: RAMX: 32K, SRAM0: 64K, SRAM1: 64K, SRAM2: 32K
83 * LPC54018: 192K @ 0x04000000
84 * LPC540xx: 192K @ 0x04000000
85 * LPC541xx: 32K @ 0x04000000
180 interrupts = <16 0>;
209 resets = <&reset NXP_SYSCON_RESET(1, 16)>;
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| /Zephyr-latest/dts/arm/st/u5/ |
| D | stm32u5a9Xj.dtsi | 13 /* 768K + 64K + 832K + 832K */
18 reg = <0x28000000 DT_SIZE_K(16)>;
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32wb-rcc.yaml | 28 - 16
47 - 16
55 (A.K.A C2HPRE)
65 - 16
73 (A.K.A SHDHPRE)
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| D | st,stm32wl-rcc.yaml | 24 - 16
32 (A.K.A C2HPRE)
42 - 16
50 (A.K.A SHDHPRE)
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| /Zephyr-latest/drivers/dma/ |
| D | dma_iproc_pax_v1.h | 34 #define PAX_DMA_MAX_DMA_SIZE_PER_BD (16 * 1024 * 1024)
36 /* ascii signature 'V' 'K' */
39 /* DMA transfers supported from 4 bytes thru 16M, size aligned to 4 bytes */
41 #define PAX_DMA_MAX_SIZE (16 * 1024 * 1024)
51 * Per-ring memory, with 8K & 4K alignment
53 * s/w need to allocate extra upto 8K to
63 uint64_t opq : 16; /*pkt_id 15:0*/
64 uint64_t res1 : 20; /*reserved 35:16*/
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| D | dma_iproc_pax_v2.h | 45 #define PAX_DMA_MEGA_LENGTH_MULTIPLE 16
53 * to make sure BD memories fall in 4K alignment.
58 * Per-ring memory, with 8K & 4K alignment
60 * s/w need to allocate extra upto 8K to
70 uint64_t opq : 16; /*pkt_id 15:0*/
71 uint64_t bdf : 16; /*reserved 31:16*/
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| D | dma_iproc_pax.h | 189 #define RM_COMM_THRESHOLD_CFG_RD_FIFO_MAX_THRESHOLD_SHIFT 16
197 #define RM_COMM_BD_FIFO_FULL_THRESHOLD_SHIFT 16
202 #define RM_COMM_VALUE_FOR_DDR_ADDR_GEN_SHIFT 16
227 #define RING_BD_READ_PTR_DDR_TIMER_VAL_SHIFT 16
233 #define RING_BD_CMPL_WR_PTR_DDR_TIMER_VAL_SHIFT 16
247 #define RM_COMM_TIMER_CONTROL_FAST_SHIFT 16
253 #define RM_COMM_TIMER_CONTROL_SLOW_SHIFT 16
285 #define RING_DDR_CONTROL_TIMER_SHIFT 16
325 /* one desc ring size( is 4K, 4K aligned */
328 /* completion ring size(bytes) is 8K, 8K aligned */
[all …]
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| /Zephyr-latest/soc/microchip/mec/mec172x/reg/ |
| D | mec172x_vbat.h | 33 /* Offset 0x08 32K Clock Source register */
41 #define MCHP_VBATR_CS_PCS_POS 16
58 #define MCHP_VBATR_CS_PCS_POS 16
64 /* 32K silicon OSC when chip powered by VBAT or VTR */
66 /* 32K external crystal when chip powered by VBAT or VTR */
68 /* 32K input pin on VTR. Switch to Silicon OSC on VBAT */
70 /* 32K input pin on VTR. Switch to crystal on VBAT */
72 /* Disable internal 32K VBAT clock source when VTR is off */
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| /Zephyr-latest/soc/microchip/mec/ |
| D | Kconfig | 40 bool "SPI flash clock rate of 16 MHz"
92 bool "SPI flash size 256K Bytes"
94 The SPI flash size is 256K Bytes.
97 bool "SPI flash size 512K Bytes"
99 The SPI flash size is 512K Bytes.
122 bool "SPI flash size 16M Bytes"
124 The SPI flash size is 16M Bytes.
147 The SPI flash size is 256K Bytes.
152 The SPI flash size is 256K Bytes.
157 The SPI flash size is 512K Bytes.
[all …]
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| /Zephyr-latest/dts/arm/gd/gd32l23x/ |
| D | gd32l233rc.dtsi | 14 reg = <0x20004000 DT_SIZE_K(16)>;
17 /* Combine SRAM0(16K) and SRAM1(16K), since its address is continuous. */
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| /Zephyr-latest/soc/st/stm32/stm32h7x/ |
| D | sections.ld | 16 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 16K;
24 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram2))) + 16K;
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| /Zephyr-latest/soc/gaisler/gr716a/ |
| D | linker.ld | 22 bootprom (rx) : ORIGIN = 0x00000000, LENGTH = 4K
23 extprom (rx) : ORIGIN = 0x01000000, LENGTH = 16M
26 RAM (rw) : ORIGIN = 0x30000000, LENGTH = 64K
27 SRAM (x) : ORIGIN = 0x31000000, LENGTH = 128K
30 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
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| /Zephyr-latest/subsys/bluetooth/crypto/ |
| D | bt_crypto.c | 19 int bt_crypto_f4(const uint8_t *u, const uint8_t *v, const uint8_t *x, uint8_t z, uint8_t res[16]) in bt_crypto_f4() argument
21 uint8_t xs[16]; in bt_crypto_f4()
27 LOG_DBG("x %s z 0x%x", bt_hex(x, 16), z); in bt_crypto_f4()
31 * AES-CMAC and X is used as the key k. in bt_crypto_f4()
42 sys_memcpy_swap(xs, x, 16); in bt_crypto_f4()
49 sys_mem_swap(res, 16); in bt_crypto_f4()
51 LOG_DBG("res %s", bt_hex(res, 16)); in bt_crypto_f4()
59 static const uint8_t salt[16] = {0x6c, 0x88, 0x83, 0x91, 0xaa, 0xf5, 0xa5, 0x38, in bt_crypto_f5()
70 uint8_t t[16], ws[32]; in bt_crypto_f5()
74 LOG_DBG("n1 %s", bt_hex(n1, 16)); in bt_crypto_f5()
[all …]
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| D | bt_crypto.h | 42 int bt_crypto_f4(const uint8_t *u, const uint8_t *v, const uint8_t *x, uint8_t z, uint8_t res[16]);
98 int bt_crypto_g2(const uint8_t u[32], const uint8_t v[32], const uint8_t x[16], const uint8_t y[16],
113 int bt_crypto_h6(const uint8_t w[16], const uint8_t key_id[4], uint8_t res[16]);
127 int bt_crypto_h7(const uint8_t salt[16], const uint8_t w[16], uint8_t res[16]);
137 * Pseudocode: `aes_cmac(key=aes_cmac(key=s, plaintext=k), plaintext=key_id)`
139 * @param[in] k (128-bit number in big endian)
147 int bt_crypto_h8(const uint8_t k[16], const uint8_t s[16], const uint8_t key_id[4],
148 uint8_t res[16]);
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| /Zephyr-latest/arch/arc/core/mpu/ |
| D | arc_mpu_v2_internal.h | 18 * 0x8 512 0x9 1k 0xA 2K 0xB 4K
19 * 0xC 8K 0xD 16K 0xE 32K 0xF 64K
20 * 0x10 128K 0x11 256K 0x12 512K 0x13 1M
21 * 0x14 2M 0x15 4M 0x16 8M 0x17 16M
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| D | arc_mpu_v6_internal.h | 21 * 0x8 512 0x9 1k 0xA 2K 0xB 4K
22 * 0xC 8K 0xD 16K 0xE 32K 0xF 64K
23 * 0x10 128K 0x11 256K 0x12 512K 0x13 1M
24 * 0x14 2M 0x15 4M 0x16 8M 0x17 16M
60 #define ARC_FEATURE_MPU_BANK_SIZE 16
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| /Zephyr-latest/boards/shields/x_nucleo_eeprma2/ |
| D | x_nucleo_eeprma2.overlay | 26 pagesize = <16>;
40 address-width = <16>;
53 address-width = <16>;
67 <&arduino_header 16 GPIO_ACTIVE_LOW>; /* U7: eeprom6 */
70 * All chip select pins have an on board 10k pull-up resistor to VCC,
74 * All hold pins are connected to VCC with a 10k pull-up, and
77 * All write-protect pins are connected to J11 with a 10k pull-up
88 pagesize = <16>;
103 address-width = <16>;
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| /Zephyr-latest/boards/snps/nsim/arc_classic/support/ |
| D | nsim_hs5x.props | 37 nsim_mmu=16
38 mmu_dtlb_entries=16
39 mmu_itlb_entries=16
42 mmu_pagesize=4K
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| D | nsim_hs6x.props | 36 nsim_mmu=16
37 mmu_dtlb_entries=16
38 mmu_itlb_entries=16
41 mmu_pagesize=4K
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| /Zephyr-latest/soc/snps/nsim/arc_classic/vpx5/ |
| D | CMakeLists.txt | 16 -Xvec_width=512 -Xvec_mem_size=256k -Xvec_mem_bank_width=16 -Xvec_max_fetch_size=16
|
