Lines Matching +full:16 +full:k
189 #define RM_COMM_THRESHOLD_CFG_RD_FIFO_MAX_THRESHOLD_SHIFT 16
197 #define RM_COMM_BD_FIFO_FULL_THRESHOLD_SHIFT 16
202 #define RM_COMM_VALUE_FOR_DDR_ADDR_GEN_SHIFT 16
227 #define RING_BD_READ_PTR_DDR_TIMER_VAL_SHIFT 16
233 #define RING_BD_CMPL_WR_PTR_DDR_TIMER_VAL_SHIFT 16
247 #define RM_COMM_TIMER_CONTROL_FAST_SHIFT 16
253 #define RM_COMM_TIMER_CONTROL_SLOW_SHIFT 16
285 #define RING_DDR_CONTROL_TIMER_SHIFT 16
325 /* one desc ring size( is 4K, 4K aligned */
328 /* completion ring size(bytes) is 8K, 8K aligned */
345 /* Total BDs in ring: 4K/8bytes = 512 BDs */
359 /* DMA transfers supported from 4 bytes thru 16M, size aligned to 4 bytes */
361 #define PAX_DMA_MAX_SIZE (16 * 1024 * 1024)
412 uint64_t opq : 16; /*pkt_id 15:0*/
413 uint64_t res : 16; /*reserved 16:31*/
414 uint64_t dma_status : 16; /*PAX DMA status 32:47*/
443 uint32_t signature:16;
467 /* Buffer descriptors, 4K aligned */
469 /* Completion descriptors, 8K aligned */