| /Zephyr-latest/boards/shields/mikroe_eth_click/ |
| D | mikroe_eth_click.overlay | 12 local-mac-address = [00 00 00 01 02 03];
13 /* Errata B7/1 specifies min 8Mhz, 20MHz max according to RM */
|
| /Zephyr-latest/boards/shields/mikroe_eth_click/boards/ |
| D | lpcxpresso55s69_lpc55s69_cpu0.overlay | 22 local-mac-address = [00 00 00 01 02 03];
23 /* Errata B7/1 specifies min 8Mhz, 20MHz max according to RM */
|
| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | nxp,mcux-rt-pinctrl.yaml | 17 nxp,speed = "100-mhz";
22 slow slew rate, and 100 MHZ speed.
115 01 PUS_1_47K_Ohm_Pull_Up — 47K Ohm Pull Up
142 - "50-mhz"
143 - "100-mhz"
144 - "150-mhz"
145 - "200-mhz"
148 00 SPEED_0_low_50MHz_ — low(50MHz)
149 01 SPEED_1_medium_100MHz_ — medium(100MHz)
150 10 SPEED_2_medium_150MHz_ — medium(150MHz)
[all …]
|
| D | nxp,imx8m-pinctrl.yaml | 105 00 SLOW — Slow Frequency Slew Rate (50Mhz)
106 01 MEDIUM — Medium Frequency Slew Rate (100Mhz)
107 10 FAST — Fast Frequency Slew Rate (150Mhz)
108 11 MAX — Max Frequency Slew Rate (200Mhz)
|
| /Zephyr-latest/boards/st/sensortile_box/doc/ |
| D | index.rst | 25 execution from Flash memory, frequency up to 120 MHz, MPU, 150
26 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
29 - 16 MHz crystal oscillator
96 driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator.
97 The system clock can be boosted to 120MHz.
98 The internal AHB/APB1/APB2 AMBA buses are all clocked at 80MHz.
164 …devnum=74, cfg=1, intf=0, path="2-2", alt=2, name="@OTP Memory /0x1FFF7000/01*0001Ke", serial="204…
165 …g=1, intf=0, path="2-2", alt=1, name="@Option Bytes /0x1FF00000/01*040 e/0x1FF01000/01*040 e", se…
|
| /Zephyr-latest/boards/nuvoton/numaker_pfm_m467/doc/ |
| D | index.rst | 13 - Core clock up to 200 MHz
30 * The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 200MHz.
91 https://www.nuvoton.com/export/resource-files/UM_NuMaker-PFM-M467_User_Manual_EN_Rev1.01.pdf
93 https://www.nuvoton.com/export/resource-files/TRM_M460_Series_EN_Rev1.01.pdf
|
| /Zephyr-latest/boards/01space/esp32c3_042_oled/doc/ |
| D | index.rst | 9 For more details see the `01space ESP32C3 0.42 OLED`_ Github repo.
17 * RISC-V SoC @ 160MHz with 4MB flash and 400kB RAM
37 The 01space ESP32C3 0.42 OLED board configuration supports the following hardware features:
70 :alt: 01space ESP32C3 0.42 OLED Pinout
72 01space ESP32C3 0.42 OLED Pinout
163 .. _`01space ESP32C3 0.42 OLED`: https://github.com/01Space/ESP32-C3-0.42LCD
|
| /Zephyr-latest/boards/st/sensortile_box_pro/doc/ |
| D | index.rst | 42 They operate at a frequency of up to 160 MHz.
44 - Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode)
48 - 1.5 DMPIS/MHz (Drystone 2.1)
49 - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ)
71 - 4 to 50 MHz crystal oscillator
73 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
75 - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by
78 - Internal 48 MHz with clock recovery
99 external memories: up to 160 MHz, MPU, 240 DMIPS and DSP
193 driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator.
[all …]
|
| /Zephyr-latest/boards/shields/esp_8266/doc/ |
| D | index.rst | 15 The simplest module that uses ESP-8266 is ESP-01. This is a generic shield
18 .. image:: esp-01.jpg
20 :alt: ESP-01
22 Pins Assignment of the ESP-01 Module
57 available at Espressif Systems web site. The ESP-01 module have up to 1MB of
66 present some tips to easily success. The ESP WIFI was tested with an ESP-01
80 you module have 26MHz crystal to detect boot fails.
|
| /Zephyr-latest/boards/nuvoton/numaker_pfm_m487/doc/ |
| D | index.rst | 13 - Core clock up to 192 MHz
32 * The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 192MHz.
91 https://www.nuvoton.com/export/resource-files/UM_NuMaker-PFM-M487_User_Manual_EN_Rev1.01.pdf
|
| /Zephyr-latest/include/zephyr/lorawan/ |
| D | lorawan.h | 86 LORAWAN_REGION_AS923, /**< Asia 923 MHz frequency band */
87 LORAWAN_REGION_AU915, /**< Australia 915 MHz frequency band */
88 LORAWAN_REGION_CN470, /**< China 470 MHz frequency band */
89 LORAWAN_REGION_CN779, /**< China 779 MHz frequency band */
90 LORAWAN_REGION_EU433, /**< Europe 433 MHz frequency band */
91 LORAWAN_REGION_EU868, /**< Europe 868 MHz frequency band */
92 LORAWAN_REGION_KR920, /**< South Korea 920 MHz frequency band */
93 LORAWAN_REGION_IN865, /**< India 865 MHz frequency band */
94 LORAWAN_REGION_US915, /**< United States 915 MHz frequency band */
95 LORAWAN_REGION_RU864, /**< Russia 864 MHz frequency band */
[all …]
|
| /Zephyr-latest/boards/st/steval_stwinbx1/doc/ |
| D | index.rst | 39 They operate at a frequency of up to 160 MHz.
41 - Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode)
45 - 1.5 DMPIS/MHz (Drystone 2.1)
46 - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ)
68 - 4 to 50 MHz crystal oscillator
70 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
72 - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by
75 - Internal 48 MHz with clock recovery
96 external memories: up to 160 MHz, MPU, 240 DMIPS and DSP
168 - **TSV912** wide-bandwidth (8 MHz) rail-to-rail I/O op-amp
[all …]
|
| /Zephyr-latest/boards/croxel/croxel_cx1825/doc/ |
| D | index.rst | 27 - Ezurio's BL654 (nRF52840 ARM Cortex-M4F processor at 64MHz)
121 https://croxeldata.s3.amazonaws.com/cx1825/CX1825-01_SCH_200424A.PDF
|
| /Zephyr-latest/boards/renesas/da14695_dk_usb/doc/ |
| D | index.rst | 24 the sleep clock is 32768 Hz. The frequency of the system clock is 32 MHz.
60 The DA14695 Development Kit USB is configured to use the 32 MHz external oscillator
72 * LED (red), = P1.01
|
| /Zephyr-latest/boards/renesas/da1469x_dk_pro/doc/ |
| D | index.rst | 25 the sleep clock is 32768 Hz. The frequency of the system clock is 32 MHz.
62 The DA1469x Development Kit Pro is configured to use the 32 MHz external oscillator
74 * LED (red), located on daughterboard = P1.01
|
| /Zephyr-latest/boards/pine64/pinetime_devkit0/ |
| D | pinetime_devkit0.dts | 95 mipi-max-frequency = <8000000>; /* 8MHz */
109 cmd2en-param = [5a 69 02 01];
197 spi-max-frequency = <8000000>; /* 8MHz */
|
| /Zephyr-latest/drivers/ieee802154/ |
| D | ieee802154_dw1000_regs.h | 170 /* Transmit Pulse Repetition Frequency = 4 Mhz */
172 /* Transmit Pulse Repetition Frequency = 16 Mhz */
174 /* Transmit Pulse Repetition Frequency = 64 Mhz */
470 * 00 = 16 symbols, 01 = 64 symbols, 10 = 1024 symbols, 11 = 4096 symbols
749 * 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz.
757 * 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz.
762 * 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz.
767 * 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz.
1752 * The system clock will run off the 19.2 MHz XTI clock until the PLL is
1753 * calibrated and locked, then it will switch over the 125 MHz PLL clock
[all …]
|
| /Zephyr-latest/boards/96boards/avenger96/doc/ |
| D | index.rst | 16 - RAM: 1024 Mbyte @ 533MHz
22 - microSD Socket: UHS-1 v3.01
66 - Up to 209 MHz (Up to 703 CoreMark®)
78 - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz
80 - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
108 - 2 × 12-bit D/A converters (1 MHz)
186 The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value
|
| /Zephyr-latest/subsys/logging/ |
| D | log_output.c | 183 char time_str[sizeof("1970-01-01T00:00:00")]; in timestamp_print()
216 char time_str[sizeof("1970-01-01 00:00:00")]; in timestamp_print()
236 char time_str[sizeof("1970-01-01T00:00:00")]; in timestamp_print()
723 /* There is no point to have frequency higher than 1MHz (ns are not in log_output_timestamp_freq_set()
|
| /Zephyr-latest/soc/altr/zephyr_nios2f/cpu/ |
| D | ghrd_10m50da.qsf | 22 # Date created = 16:01:48 April 27, 2016
43 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:01:48 APRIL 27, 2016"
200 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[0]
201 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[2]
202 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_pb[1]
331 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[4]
332 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[1]
333 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[7]
334 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[2]
|
| /Zephyr-latest/boards/96boards/carbon/doc/ |
| D | stm32f401xe.rst | 51 - 84 MHz max CPU frequency
203 32.768 kHz. The frequency of the main clock is 16 MHz.
283 …er=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574…
284 …r=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial=…
285 …ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574…
286 …evnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", ser…
|
| /Zephyr-latest/drivers/adc/ |
| D | adc_sam.c | 302 LOG_ERR("Invalid ADC clock frequency %d (1MHz < freq < 22Mhz)", frequency); in adc_sam_init()
334 * and IBCTL = 01 for a sampling frequency between 500 kHz and 1 MHz. in adc_sam_init()
|
| /Zephyr-latest/drivers/input/ |
| D | input_stmpe811.c | 97 * ADC clock speed: 3.25 MHz
99 * - 00 : 1.625 MHz
100 * - 01 : 3.25 MHz
101 * - 10 : 6.5 MHz
102 * - 11 : 6.5 MHz
|
| /Zephyr-latest/include/zephyr/drivers/rtc/ |
| D | maxim_ds3231.h | 272 * alarm times will fall within 1978-01 since 1978-01-01
331 * running at between 1 kHz and 1 MHz, allowing for
341 * and 1 MHz and be itself synchronized with the primary system time
|
| /Zephyr-latest/boards/phytec/phyboard_polis/doc/ |
| D | index.rst | 186 The M4 Core is configured to run at a 400 MHz clock speed.
313 ``PEB-EVAL-01`` Shield, which can be directly connected to the JLink.
316 .. figure:: img/PEB-EVAL-01.jpg
317 :alt: PEB-EVAL-01
320 PEB-EVAL-01
|
