| /Zephyr-latest/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/ |
| D | service_a_1.c | 4 * SPDX-License-Identifier: Apache-2.0
9 * This code is auto-generated from the Excel Workbook
24 #define BT_UUID_SERVICE_A BT_UUID_DECLARE_16(0xa00a)
29 #define BT_UUID_VALUE_V1 BT_UUID_DECLARE_16(0xb001)
34 #define BT_UUID_VALUE_V2 BT_UUID_DECLARE_16(0xb002)
39 #define BT_UUID_VALUE_V3 BT_UUID_DECLARE_16(0xb003)
41 static uint8_t value_v1_value = 0x01;
45 '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8',
46 '8', '9', '9', '9', '9', '9', '0', '0', '0', '0', '0', '1', '1',
49 '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9',
[all …]
|
| /Zephyr-latest/drivers/ieee802154/ |
| D | ieee802154_rf2xx_regs.h | 1 /* ieee802154_rf2xx_regs.h - ATMEL RF2XX transceiver registers */
6 * SPDX-License-Identifier: Apache-2.0
12 /*- Definitions ------------------------------------------------------------*/
27 #define RF2XX_RSSI_BPSK_20 -100
28 #define RF2XX_RSSI_BPSK_40 -99
29 #define RF2XX_RSSI_OQPSK_SIN_RC_100 -98
30 #define RF2XX_RSSI_OQPSK_SIN_250 -97
31 #define RF2XX_RSSI_OQPSK_RC_250 -97
33 /*- Types ------------------------------------------------------------------*/
34 #define RF2XX_TRX_STATUS_REG 0x01
[all …]
|
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32h5_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
43 #define STM32_CLOCK_BUS_AHB1 0x088
44 #define STM32_CLOCK_BUS_AHB2 0x08C
45 #define STM32_CLOCK_BUS_AHB4 0x094
46 #define STM32_CLOCK_BUS_APB1 0x09c
47 #define STM32_CLOCK_BUS_APB1_2 0x0A0
48 #define STM32_CLOCK_BUS_APB2 0x0A4
49 #define STM32_CLOCK_BUS_APB3 0x0A8
54 #define STM32_CLOCK_REG_MASK 0xFFU
55 #define STM32_CLOCK_REG_SHIFT 0U
[all …]
|
| D | npcm_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
12 #define NPCM_CLOCK_PWM_I (NPCM_CLOCK_GROUP_OFFSET(0) + 0)
13 #define NPCM_CLOCK_PWM_J (NPCM_CLOCK_GROUP_OFFSET(0) + 1)
14 #define NPCM_CLOCK_I3CI (NPCM_CLOCK_GROUP_OFFSET(0) + 2)
15 #define NPCM_CLOCK_UART3 (NPCM_CLOCK_GROUP_OFFSET(0) + 5)
16 #define NPCM_CLOCK_UART2 (NPCM_CLOCK_GROUP_OFFSET(0) + 6)
17 #define NPCM_CLOCK_SPIM (NPCM_CLOCK_GROUP_OFFSET(1) + 0)
23 #define NPCM_CLOCK_MFT3 (NPCM_CLOCK_GROUP_OFFSET(1) + 7)
24 #define NPCM_CLOCK_PWM_A (NPCM_CLOCK_GROUP_OFFSET(2) + 0)
31 #define NPCM_CLOCK_PWM_H (NPCM_CLOCK_GROUP_OFFSET(2) + 7)
[all …]
|
| D | stm32h7rs_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
44 #define STM32_CLOCK_BUS_AHB1 0x138
45 #define STM32_CLOCK_BUS_AHB2 0x13C
46 #define STM32_CLOCK_BUS_AHB3 0x158
47 #define STM32_CLOCK_BUS_AHB4 0x140
48 #define STM32_CLOCK_BUS_AHB5 0x134
49 #define STM32_CLOCK_BUS_APB1 0x148
50 #define STM32_CLOCK_BUS_APB1_2 0x14C
51 #define STM32_CLOCK_BUS_APB2 0x150
52 #define STM32_CLOCK_BUS_APB4 0x154
[all …]
|
| D | stm32h7_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
42 #define STM32_CLOCK_BUS_AHB3 0x0D4
43 #define STM32_CLOCK_BUS_AHB1 0x0D8
44 #define STM32_CLOCK_BUS_AHB2 0x0DC
45 #define STM32_CLOCK_BUS_AHB4 0x0E0
46 #define STM32_CLOCK_BUS_APB3 0x0E4
47 #define STM32_CLOCK_BUS_APB1 0x0E8
48 #define STM32_CLOCK_BUS_APB1_2 0x0EC
49 #define STM32_CLOCK_BUS_APB2 0x0F0
50 #define STM32_CLOCK_BUS_APB4 0x0F4
[all …]
|
| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_b91.c | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/b91-pinctrl.h>
17 * gpio_en: PORT_A[0-7]
18 * gpio_en + 1*8: PORT_B[0-7]
19 * gpio_en + 2*8: PORT_C[0-7]
20 * gpio_en + 3*8: PORT_D[0-7]
21 * gpio_en + 4*8: PORT_E[0-7]
22 * gpio_en + 5*8: PORT_F[0-7]
24 #define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \
30 * pin_mux: PORT_A[0-3]
[all …]
|
| /Zephyr-latest/dts/arm/nuvoton/npcx/ |
| D | npcx-miwus-wui-map.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 npcx-miwus-wui-map {
10 compatible = "nuvoton,npcx-miwu-wui-map";
12 /* MIWU table 0 */
14 wui_io80: wui0-1-0 {
15 miwus = <&miwu0 0 0>; /* GPIO80 */
17 wui_io81: wui0-1-1 {
18 miwus = <&miwu0 0 1>; /* GPIO81 */
20 wui_io82: wui0-1-2 {
21 miwus = <&miwu0 0 2>; /* GPIO82 */
[all …]
|
| /Zephyr-latest/boards/nxp/lpcxpresso55s69/ |
| D | board.c | 3 * SPDX-License-Identifier: Apache-2.0
18 * Flexcomm 6 and 7 are connected to codec on board, and shared signal in lpcxpresso_55s69_board_init()
23 /* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm 7 */ in lpcxpresso_55s69_board_init()
24 SYSCTL->SHAREDCTRLSET[0] = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(7) | in lpcxpresso_55s69_board_init()
25 SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(7); in lpcxpresso_55s69_board_init()
28 /* Select Data in from Transmit I2S - Flexcomm 7 */ in lpcxpresso_55s69_board_init()
29 SYSCTL->SHAREDCTRLSET[0] |= SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(7); in lpcxpresso_55s69_board_init()
30 /* Enable Transmit I2S - Flexcomm 7 for Shared Data Out */ in lpcxpresso_55s69_board_init()
31 SYSCTL->SHAREDCTRLSET[0] |= SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(1); in lpcxpresso_55s69_board_init()
34 /* Set Receive I2S - Flexcomm 6 SCK, WS from shared signal set 0 */ in lpcxpresso_55s69_board_init()
[all …]
|
| /Zephyr-latest/drivers/charger/ |
| D | bq24190.h | 4 * SPDX-License-Identifier: Apache-2.0
11 #define BQ24190_REG_ISC 0x00
12 #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7)
13 #define BQ24190_REG_ISC_EN_HIZ_SHIFT 7
16 #define BQ24190_REG_ISC_IINLIM_MASK GENMASK(2, 0)
18 /* Power-On Configuration */
19 #define BQ24190_REG_POC 0x01
20 #define BQ24190_REG_POC_RESET_MASK BIT(7)
21 #define BQ24190_REG_POC_RESET_SHIFT 7
27 #define BQ24190_REG_POC_CHG_CONFIG_DISABLE 0x0
[all …]
|
| /Zephyr-latest/tests/drivers/spi/spi_loopback/boards/ |
| D | nrf54h20dk_nrf54h20_cpuapp_fast.overlay | 4 * SPDX-License-Identifier: Apache-2.0
10 psels = <NRF_PSEL(SPIM_SCK, 7, 3)>,
11 <NRF_PSEL(SPIM_MISO, 7, 6)>,
12 <NRF_PSEL(SPIM_MOSI, 7, 7)>;
18 psels = <NRF_PSEL(SPIM_SCK, 7, 3)>,
19 <NRF_PSEL(SPIM_MISO, 7, 6)>,
20 <NRF_PSEL(SPIM_MOSI, 7, 7)>;
21 low-power-enable;
32 pinctrl-0 = <&spi120_default>;
33 pinctrl-1 = <&spi120_sleep>;
[all …]
|
| /Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/ |
| D | npcx4-miwus-wui-map.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 /* Common Wake-Up Unit Input (WUI) mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-wui-map.dtsi>
10 /* Specific Wake-Up Unit Input (WUI) mapping configurations in npcx4 series */
13 npcx-miwus-wui-map {
14 compatible = "nuvoton,npcx-miwu-wui-map";
16 /* MIWU table 0 */
18 wui_ioe7: wui0-8-7 {
19 miwus = <&miwu0 7 7>; /* GPIOE7 */
24 wui_io13: wui1-2-3 {
[all …]
|
| /Zephyr-latest/tests/drivers/uart/uart_async_api/boards/ |
| D | nrf54h20dk_nrf54h20_common.dtsi | 1 /* SPDX-License-Identifier: Apache-2.0 */
6 psels = <NRF_PSEL(UART_TX, 0, 6)>;
9 psels = <NRF_PSEL(UART_RX, 0, 7)>;
10 bias-pull-up;
16 psels = <NRF_PSEL(UART_TX, 0, 6)>,
17 <NRF_PSEL(UART_RX, 0, 7)>;
18 low-power-enable;
23 psels = <NRF_PSEL(UART_TX, 7, 7)>;
26 psels = <NRF_PSEL(UART_RX, 7, 4)>;
27 bias-pull-up;
[all …]
|
| /Zephyr-latest/drivers/sensor/st/lsm6dsl/ |
| D | lsm6dsl.h | 1 /* sensor_lsm6dsl.h - header file for LSM6DSL accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
28 #define LSM6DSL_REG_FUNC_CFG_ACCESS 0x01
29 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7)
30 #define LSM6DSL_SHIFT_FUNC_CFG_EN 7
34 #define LSM6DSL_REG_SENSOR_SYNC_TIME_FRAME 0x04
36 BIT(1) | BIT(0))
37 #define LSM6DSL_SHIFT_SENSOR_SYNC_TIME_FRAME_TPH 0
39 #define LSM6DSL_REG_SENSOR_SYNC_RES_RATIO 0x05
40 #define LSM6DSL_MASK_SENSOR_SYNC_RES_RATIO (BIT(1) | BIT(0))
[all …]
|
| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | ti-cc32xx-pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole TI CC32XX pin configuration information is encoded in a 32-bit
13 * - 31..22: Reserved
14 * - 21..16: Pin.
15 * - 15..10: Reserved.
16 * - 9: Pull-down flag.
17 * - 8: Pull-up flag.
18 * - 7..5: Drive strength.
19 * - 4: Enable open-drain flag.
20 * - 3..0: Configuration mode
[all …]
|
| /Zephyr-latest/drivers/audio/ |
| D | tlv320dac310x.h | 4 * SPDX-License-Identifier: Apache-2.0
15 #define PAGE_CONTROL_ADDR 0
18 #define SOFT_RESET_ADDR (struct reg_addr){0, 1}
21 #define NDAC_DIV_ADDR (struct reg_addr){0, 11}
22 #define NDAC_POWER_UP BIT(7)
23 #define NDAC_POWER_UP_MASK BIT(7)
24 #define NDAC_DIV_MASK BIT_MASK(7)
27 #define MDAC_DIV_ADDR (struct reg_addr){0, 12}
28 #define MDAC_POWER_UP BIT(7)
29 #define MDAC_POWER_UP_MASK BIT(7)
[all …]
|
| /Zephyr-latest/samples/modules/cmsis_dsp/moving_average/ |
| D | sample.yaml | 7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
[all …]
|
| /Zephyr-latest/dts/arm/infineon/cat3/xmc/ |
| D | xmc4500_F100x1024-intc.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
10 XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */
11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
[all …]
|
| D | xmc4700_F144x2048-intc.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
10 XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */
11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
[all …]
|
| /Zephyr-latest/drivers/sensor/st/lps25hb/ |
| D | lps25hb.h | 1 /* sensor_lps25hb.h - header file for LPS25HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
18 #define LPS25HB_REG_WHO_AM_I 0x0F
19 #define LPS25HB_VAL_WHO_AM_I 0xBD
21 #define LPS25HB_REG_REF_P_XL 0x08
22 #define LPS25HB_REG_REF_P_L 0x09
23 #define LPS25HB_REG_REF_P_H 0x0A
25 #define LPS25HB_REG_RES_CONF 0x10
28 #define LPS25HB_MASK_RES_CONF_AVGP (BIT(1) | BIT(0))
29 #define LPS25HB_SHIFT_RES_CONF_AVGP 0
[all …]
|
| /Zephyr-latest/boards/andestech/adp_xc7k_ae350/ |
| D | adp_xc7k_ae350.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "Andes ADP-XC7K AE350";
17 gpio-0 = &gpio0;
18 counter-0 = &pit0;
19 i2c-0 = &i2c0;
23 eeprom-0 = &eeprom;
28 zephyr,shell-uart = &uart1;
31 zephyr,flash-controller = &mx25u16;
[all …]
|
| /Zephyr-latest/boards/enjoydigital/litex_vexriscv/doc/img/ |
| D | symbiflow.svg | 1 …0" y="0" viewBox="0 0 532.8 134.4" xml:space="preserve"><style>.st0{fill:#5a2ab5}</style><path cla…
|
| /Zephyr-latest/drivers/sensor/st/lsm9ds0_gyro/ |
| D | lsm9ds0_gyro.h | 1 /* sensor_lsm9ds0_gyro.h - header file for LSM9DS0 gyroscope sensor driver */
6 * SPDX-License-Identifier: Apache-2.0
19 #define LSM9DS0_GYRO_REG_WHO_AM_I_G 0x0F
20 #define LSM9DS0_GYRO_VAL_WHO_AM_I_G 0xD4
22 #define LSM9DS0_GYRO_REG_CTRL_REG1_G 0x20
23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
33 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0)
34 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_YEN 0
36 #define LSM9DS0_GYRO_REG_CTRL_REG2_G 0x21
40 BIT(0))
[all …]
|
| /Zephyr-latest/drivers/sensor/maxim/max30101/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
16 range 0 7
17 default 0
21 setting this register. Set to 0 for no averaging.
22 0 = 1 sample (no averaging)
29 7 = 32 samples
42 range 0 15
43 default 0
63 bool "Multi-LED mode"
65 Set to operate in multi-LED mode. The green, red, and/or IR LED
[all …]
|
| /Zephyr-latest/samples/subsys/fs/zms/ |
| D | README.rst | 1 .. zephyr:code-sample:: zms
3 :relevant-api: zms_high_level_api
15 #. A binary blob representing a key/value pair: stored at id=0xbeefdead,
16 data={0xDE, 0xAD, 0xBE, 0xEF, 0xDE, 0xAD, 0xBE, 0xEF}
40 .. zephyr-app-commands::
41 :zephyr-app: samples/subsys/fs/zms
51 .. code-block:: console
53 *** Booting Zephyr OS build v3.7.0-2383-g624f75400242 ***
55 [00:00:00.000,000] <inf> fs_zms: alloc wra: 0, fc0
56 [00:00:00.000,000] <inf> fs_zms: data wra: 0, 0
[all …]
|
