Lines Matching +full:0 +full:- +full:7

4  * SPDX-License-Identifier: Apache-2.0
44 #define STM32_CLOCK_BUS_AHB1    0x138
45 #define STM32_CLOCK_BUS_AHB2    0x13C
46 #define STM32_CLOCK_BUS_AHB3    0x158
47 #define STM32_CLOCK_BUS_AHB4    0x140
48 #define STM32_CLOCK_BUS_AHB5    0x134
49 #define STM32_CLOCK_BUS_APB1    0x148
50 #define STM32_CLOCK_BUS_APB1_2  0x14C
51 #define STM32_CLOCK_BUS_APB2    0x150
52 #define STM32_CLOCK_BUS_APB4    0x154
53 #define STM32_CLOCK_BUS_APB5    0x144
57 #define STM32_CLOCK_REG_MASK    0xFFU
58 #define STM32_CLOCK_REG_SHIFT   0U
59 #define STM32_CLOCK_SHIFT_MASK  0x1FU
61 #define STM32_CLOCK_MASK_MASK   0x7U
63 #define STM32_CLOCK_VAL_MASK    0x7U
69  * - reg   (0/1)           [ 0 : 7 ]
70  * - shift (0..31)         [ 8 : 12 ]
71  * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
72  * - val   (0..3)          [ 16 : 18 ]
77  * @param val Clock value (0, 1, 2 or 3).
86 #define D1CCIPR_REG		0x4C
87 #define D2CCIPR_REG		0x50
88 #define D3CCIPR_REG		0x54
89 #define D4CCIPR_REG		0x58
92 #define BDCR_REG		0x70
95 #define CFGR_REG                0x10
102 #define FMC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG)
110 #define USART234578_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIPR_REG)
111 #define SPI23_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 4, D2CCIPR_REG)
115 #define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIPR_REG)
119 #define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG)
120 #define SPI45_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 4, D3CCIPR_REG)
121 #define SPI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 8, D3CCIPR_REG)
122 #define SAI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 16, D3CCIPR_REG)
123 #define SAI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 20, D3CCIPR_REG)
126 #define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 0, D4CCIPR_REG)
127 #define SPI6_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 4, D4CCIPR_REG)
128 #define LPTIM23_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 8, D4CCIPR_REG)
129 #define LPTIM45_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 12, D4CCIPR_REG)
135 #define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x7, 22, CFGR_REG)
136 #define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0xF, 18, CFGR_REG)
137 #define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x7, 29, CFGR_REG)
138 #define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0xF, 25, CFGR_REG)
147 #define MCO_PRE_DIV_7 7