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4  * SPDX-License-Identifier: Apache-2.0
11 #define BQ24190_REG_ISC              0x00
12 #define BQ24190_REG_ISC_EN_HIZ_MASK  BIT(7)
13 #define BQ24190_REG_ISC_EN_HIZ_SHIFT 7
16 #define BQ24190_REG_ISC_IINLIM_MASK  GENMASK(2, 0)
18 /* Power-On Configuration */
19 #define BQ24190_REG_POC                    0x01
20 #define BQ24190_REG_POC_RESET_MASK         BIT(7)
21 #define BQ24190_REG_POC_RESET_SHIFT        7
27 #define BQ24190_REG_POC_CHG_CONFIG_DISABLE 0x0
28 #define BQ24190_REG_POC_CHG_CONFIG_CHARGE  0x1
29 #define BQ24190_REG_POC_CHG_CONFIG_OTG     0x2
30 #define BQ24190_REG_POC_CHG_CONFIG_OTG_ALT 0x3
35 #define BQ24190_REG_POC_BOOST_LIM_MASK     BIT(0)
36 #define BQ24190_REG_POC_BOOST_LIM_SHIFT    0
39 #define BQ24190_REG_CCC                   0x02
40 #define BQ24190_REG_CCC_ICHG_MASK         GENMASK(7, 2)
46 #define BQ24190_REG_CCC_FORCE_20PCT_MASK  BIT(0)
47 #define BQ24190_REG_CCC_FORCE_20PCT_SHIFT 0
49 /* Pre-charge/Termination Current Cntl */
50 #define BQ24190_REG_PCTCC                   0x03
51 #define BQ24190_REG_PCTCC_IPRECHG_MASK      GENMASK(7, 4)
57 #define BQ24190_REG_PCTCC_ITERM_MASK        GENMASK(3, 0)
58 #define BQ24190_REG_PCTCC_ITERM_SHIFT       0
65 #define BQ24190_REG_CVC                0x04
66 #define BQ24190_REG_CVC_VREG_MASK      GENMASK(7, 2)
74 #define BQ24190_REG_CVC_VRECHG_MASK    BIT(0)
75 #define BQ24190_REG_CVC_VRECHG_SHIFT   0
78 #define BQ24190_REG_CTTC                  0x05
79 #define BQ24190_REG_CTTC_EN_TERM_MASK     BIT(7)
80 #define BQ24190_REG_CTTC_EN_TERM_SHIFT    7
89 #define BQ24190_REG_CTTC_JEITA_ISET_MASK  BIT(0)
90 #define BQ24190_REG_CTTC_JEITA_ISET_SHIFT 0
93 #define BQ24190_REG_ICTRC                0x06
94 #define BQ24190_REG_ICTRC_BAT_COMP_MASK  GENMASK(7, 5)
98 #define BQ24190_REG_ICTRC_TREG_MASK      GENMASK(1, 0)
99 #define BQ24190_REG_ICTRC_TREG_SHIFT     0
102 #define BQ24190_REG_MOC                      0x07
103 #define BQ24190_REG_MOC_DPDM_EN_MASK         BIT(7)
104 #define BQ24190_REG_MOC_DPDM_EN_SHIFT        7
111 #define BQ24190_REG_MOC_INT_MASK_MASK        GENMASK(1, 0)
112 #define BQ24190_REG_MOC_INT_MASK_SHIFT       0
115 #define BQ24190_REG_SS                  0x08
116 #define BQ24190_REG_SS_VBUS_STAT_MASK   GENMASK(7, 6)
120 #define BQ24190_CHRG_STAT_NOT_CHRGING   0x0
121 #define BQ24190_CHRG_STAT_PRECHRG       0x1
122 #define BQ24190_CHRG_STAT_FAST_CHRG     0x2
123 #define BQ24190_CHRG_STAT_CHRG_TERM     0x3
130 #define BQ24190_REG_SS_VSYS_STAT_MASK   BIT(0)
131 #define BQ24190_REG_SS_VSYS_STAT_SHIFT  0
134 #define BQ24190_REG_F                      0x09
135 #define BQ24190_REG_F_WATCHDOG_FAULT_MASK  BIT(7)
136 #define BQ24190_REG_F_WATCHDOG_FAULT_SHIFT 7
141 #define BQ24190_CHRG_FAULT_INPUT_FAULT     0x1
142 #define BQ24190_CHRG_FAULT_TSHUT           0x2
143 #define BQ24190_CHRG_SAFETY_TIMER          0x3
146 #define BQ24190_REG_F_NTC_FAULT_MASK       GENMASK(2, 0)
147 #define BQ24190_REG_F_NTC_FAULT_SHIFT      0
148 #define BQ24190_NTC_FAULT_TS1_COLD         0x1
149 #define BQ24190_NTC_FAULT_TS1_HOT          0x2
150 #define BQ24190_NTC_FAULT_TS2_COLD         0x3
151 #define BQ24190_NTC_FAULT_TS2_HOT          0x4
152 #define BQ24190_NTC_FAULT_TS1_TS2_COLD     0x5
153 #define BQ24190_NTC_FAULT_TS1_TS2_HOT      0x6
156 #define BQ24190_REG_VPRS                  0x0A
159 #define BQ24190_REG_VPRS_PN_24190         0x4
160 #define BQ24190_REG_VPRS_PN_24192         0x5 /* Also 24193, 24196 */
161 #define BQ24190_REG_VPRS_PN_24192I        0x3
164 #define BQ24190_REG_VPRS_DEV_REG_MASK     GENMASK(1, 0)
165 #define BQ24190_REG_VPRS_DEV_REG_SHIFT    0