Searched +full:0 +full:- +full:64 (Results 1 – 25 of 1163) sorted by relevance
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| /Zephyr-latest/dts/arm/atmel/ |
| D | same5x.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
13 compatible = "atmel,sam0-gmac";
14 reg = <0x42000800 0x400>;
15 interrupts = <84 0>;
16 interrupt-names = "gmac";
19 num-queues = <1>;
20 local-mac-address = [00 00 00 00 00 00];
24 compatible = "atmel,sam-mdio";
25 reg = <0x42000800 0x400>;
28 #address-cells = <1>;
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| /Zephyr-latest/arch/sparc/core/ |
| D | interrupt_trap.S | 2 * Copyright (c) 2019-2020 Cobham Gaisler AB
4 * SPDX-License-Identifier: Apache-2.0
19 * - IU state is saved and restored
30 * - Do not re-execute the causing (ta) instruction at trap exit.
31 * - A dedicated interrupt request level (0x8d) is used.
32 * - z_sparc_enter_irq() knows how to interpret this interrupt request level.
38 set 0x8d, %l3
53 sll %g2, (CONFIG_SPARC_NWIN-1), %g3
65 std %l0, [%sp + 0x00]
66 std %l2, [%sp + 0x08]
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| /Zephyr-latest/tests/kernel/timer/timer_api/src/ |
| D | timer_convert.c | 4 * SPDX-License-Identifier: Apache-2.0
26 int precision; /* 32 or 64 */
51 TESTFUNC(ms, cyc, floor, 64)
53 TESTFUNC(ms, cyc, near, 64)
55 TESTFUNC(ms, cyc, ceil, 64)
57 TESTFUNC(ms, ticks, floor, 64)
59 TESTFUNC(ms, ticks, near, 64)
61 TESTFUNC(ms, ticks, ceil, 64)
63 TESTFUNC(us, cyc, floor, 64)
65 TESTFUNC(us, cyc, near, 64)
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| /Zephyr-latest/dts/bindings/can/ |
| D | bosch,m_can-base.yaml | 3 include: [can-fd-controller.yaml]
6 bosch,mram-cfg:
12 <offset std-filter-elements ext-filter-elements rx-fifo0-elements rx-fifo1-elements
13 rx-buffer-elements tx-event-fifo-elements tx-buffer-elements>
16 from. This is normally set to 0x0 when using a non-shared message RAM. The remaining cells
20 11-bit Filter 0-128 elements / 0-128 words
21 29-bit Filter 0-64 elements / 0-128 words
22 Rx FIFO 0 0-64 elements / 0-1152 words
23 Rx FIFO 1 0-64 elements / 0-1152 words
24 Rx Buffers 0-64 elements / 0-1152 words
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| /Zephyr-latest/dts/riscv/starfive/ |
| D | jh7110-visionfive-v2.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
8 #include "jh7110-clk.dtsi"
9 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 S7_0: cpu@0 {
25 reg = <0>;
28 cpu0_intc: interrupt-controller {
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| D | starfive_jh7100_beagle_v.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,freedom-u74-arty";
14 model = "sifive,freedom-u74-arty";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 compatible = "starfive,fu74-g000";
20 cpu@0 {
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| /Zephyr-latest/dts/arm64/nxp/ |
| D | nxp_mimx95_a55.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm64/armv8-a.dtsi>
10 #include <zephyr/dt-bindings/clock/imx95_clock.h>
11 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
16 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu@0 {
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| D | nxp_mimx8mm_a53.dtsi | 2 * Copyright 2020-2022,2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm64/armv8-a.dtsi>
10 #include <zephyr/dt-bindings/clock/imx_ccm.h>
11 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 zephyr,shell-uart = &uart2;
24 #address-cells = <1>;
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| D | nxp_mimx8mp_a53.dtsi | 2 * Copyright 2020-2022,2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm64/armv8-a.dtsi>
10 #include <zephyr/dt-bindings/clock/imx_ccm.h>
11 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
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| D | nxp_mimx8mn_a53.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm64/armv8-a.dtsi>
10 #include <zephyr/dt-bindings/clock/imx_ccm.h>
11 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 zephyr,shell-uart = &uart2;
24 #address-cells = <1>;
25 #size-cells = <0>;
[all …]
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| /Zephyr-latest/include/zephyr/arch/x86/intel64/ |
| D | thread.h | 3 * SPDX-License-Identifier: Apache-2.0
9 #define X86_THREAD_FLAG_ALL 0x01 /* _thread_arch.flags: entire state saved */
12 * GDT selectors - these must agree with the GDT layout in locore.S.
15 #define X86_KERNEL_CS_32 0x08 /* 32-bit kernel code */
16 #define X86_KERNEL_DS_32 0x10 /* 32-bit kernel data */
17 #define X86_KERNEL_CS 0x18 /* 64-bit kernel code */
18 #define X86_KERNEL_DS 0x20 /* 64-bit kernel data */
19 #define X86_USER_CS_32 0x28 /* 32-bit user data (unused) */
20 #define X86_USER_DS 0x30 /* 64-bit user mode data */
21 #define X86_USER_CS 0x38 /* 64-bit user mode code */
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| /Zephyr-latest/boards/snps/nsim/arc_classic/support/ |
| D | nsim_hs6x.props | 1 maxlastpc=0
2 trace_enabled=0
4 nsim_isa_core=0
5 arcver=0x70
7 nsim_isa_uarch_rev_major=0
8 nsim_isa_uarch_rev_minor=0
12 nsim_isa_big_endian=0
16 nsim_isa_pc_size=64
17 nsim_isa_addr_size=64
18 nsim_isa_shift_option=0
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| D | mdb_hs_smp.args | 1 -arcv2hs
2 -core2
3 -rgf_num_banks=2
4 -rgf_banked_regs=32
5 -rgf_num_wr_ports=2
6 -Xatomic
7 -Xll64
8 -Xunaligned
9 -Xcode_density
10 -Xdiv_rem=radix4
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| D | mdb_hs5x_smp.args | 1 -arcv3hs
2 -core0
3 -Xdual_issue
4 -uarch_rev=0:0
5 -rgf_num_banks=1
6 -rgf_num_wr_ports=2
7 -lpc_width=0
8 -Xatomic=2
9 -Xll64
10 -Xunaligned
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| D | mdb_hs5x_smp_12cores.args | 1 -arcv3hs
2 -core0
3 -Xdual_issue
4 -uarch_rev=0:0
5 -rgf_num_banks=1
6 -rgf_num_wr_ports=2
7 -lpc_width=0
8 -Xatomic=2
9 -Xll64
10 -Xunaligned
[all …]
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | soc_pmc.c | 3 * SPDX-License-Identifier: Apache-2.0
24 PMC->PMC_PCER0 = BIT(id); in soc_pmc_peripheral_enable()
26 } else if (id < 64) { in soc_pmc_peripheral_enable()
27 PMC->PMC_PCER1 = BIT(id & 0x1F); in soc_pmc_peripheral_enable()
29 #if ID_PERIPH_COUNT > 64 in soc_pmc_peripheral_enable()
41 PMC->PMC_PCDR0 = BIT(id); in soc_pmc_peripheral_disable()
43 } else if (id < 64) { in soc_pmc_peripheral_disable()
44 PMC->PMC_PCDR1 = BIT(id & 0x1F); in soc_pmc_peripheral_disable()
46 #if ID_PERIPH_COUNT > 64 in soc_pmc_peripheral_disable()
58 return (PMC->PMC_PCSR0 & BIT(id)) != 0; in soc_pmc_peripheral_is_enabled()
[all …]
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| /Zephyr-latest/samples/subsys/fs/fs_sample/boards/ |
| D | nrf52840dk_nrf52840.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 /* Because FAT FS needs at least 64kiB partition and default
9 * partitions to get at least 64KiB.
10 * This overlay removes image slot partitions and strips each of 64kiB,
11 * and removes the storage partition to add the additional 2*64kiB to
14 /delete-node/ &slot0_partition;
15 /delete-node/ &slot1_partition;
16 /delete-node/ &storage_partition;
21 compatible = "fixed-partitions";
22 #address-cells = <1>;
[all …]
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_kv5xf512vlx24.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 /* 64KB ITCM @ 0, 64KB DTCM @ 20000000 */
14 compatible = "mmio-sram";
15 reg = <0x20000000 DT_SIZE_K(64)>;
21 compatible = "soc-nv-flash";
22 reg = <0x10000000 DT_SIZE_K(512)>;
23 erase-block-size = <DT_SIZE_K(8)>;
24 write-block-size = <8>;
|
| D | nxp_imx95_m7.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/clock/imx95_clock.h>
9 #include <dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
17 cpu@0 {
19 compatible = "arm,cortex-m7";
20 reg = <0>;
22 #address-cells = <1>;
[all …]
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| D | nxp_imx8m_m4.dtsi | 2 * Copyright (c) 2021, Kwon Tae-young
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/clock/imx_ccm.h>
9 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu@0 {
20 compatible = "arm,cortex-m4";
[all …]
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| D | nxp_imx8ml_m7.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/clock/imx_ccm.h>
9 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
17 cpu@0 {
19 compatible = "arm,cortex-m7";
20 reg = <0>;
21 #address-cells = <1>;
[all …]
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| /Zephyr-latest/tests/cmake/overlays/soc_folder_overlay/ |
| D | testcase.yaml | 3 - cmake
7 - native_sim
8 - native_sim/native/64
10 - native_sim
11 - native_sim/native/64
13 - CONFIG_TEST_TYPE=0
16 - native_sim
17 - native_sim/native/64
19 - native_sim
20 - native_sim/native/64
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| /Zephyr-latest/include/zephyr/toolchain/ |
| D | xcc_missing_defs.h | 4 * SPDX-License-Identifier: Apache-2.0
43 #define __LONG_LONG_WIDTH__ 64
50 #define __INTMAX_WIDTH__ 64
52 #define __UINTMAX_MAX__ 0xffffffffffffffffULL
53 #define __UINTMAX_WIDTH__ 64
64 #define __INTPTR_MAX__ 0x7fffffffL
69 #define __PTRDIFF_MAX__ 0x7fffffffL
73 #define __UINTPTR_MAX__ 0xffffffffLU
81 #define __SIZE_MAX__ 0xffffffffU
90 #define __INT8_MAX__ 0x7f
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| /Zephyr-latest/dts/arm/renesas/ra/ra4/ |
| D | ra4-cm33-common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
10 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu@0 {
20 compatible = "arm,cortex-m33";
21 reg = <0>;
22 #address-cells = <1>;
[all …]
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| /Zephyr-latest/dts/arm/renesas/ra/ra6/ |
| D | ra6-cm33-common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
10 #include <zephyr/dt-bindings/clock/ra_clock.h>
11 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu@0 {
21 compatible = "arm,cortex-m33";
22 reg = <0>;
[all …]
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