Lines Matching +full:0 +full:- +full:64
5 * SPDX-License-Identifier: Apache-2.0
8 #include "jh7110-clk.dtsi"
9 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 S7_0: cpu@0 {
25 reg = <0>;
28 cpu0_intc: interrupt-controller {
29 compatible = "riscv,cpu-intc";
30 interrupt-controller;
31 #interrupt-cells = <1>;
38 d-cache-block-size = <64>;
39 d-cache-sets = <64>;
40 d-cache-size = <32768>;
41 d-tlb-sets = <1>;
42 d-tlb-size = <40>;
43 i-cache-block-size = <64>;
44 i-cache-sets = <64>;
45 i-cache-size = <32768>;
46 i-tlb-sets = <1>;
47 i-tlb-size = <40>;
48 mmu-type = "riscv,sv39";
49 next-level-cache = <&ccache>;
50 reg = <0x1>;
52 tlb-spilt;
53 cpu1_intc: interrupt-controller {
54 compatible = "riscv,cpu-intc";
55 #interrupt-cells = <1>;
56 interrupt-controller;
63 d-cache-block-size = <64>;
64 d-cache-sets = <64>;
65 d-cache-size = <32768>;
66 d-tlb-sets = <1>;
67 d-tlb-size = <40>;
68 i-cache-block-size = <64>;
69 i-cache-sets = <64>;
70 i-cache-size = <32768>;
71 i-tlb-sets = <1>;
72 i-tlb-size = <40>;
73 mmu-type = "riscv,sv39";
74 next-level-cache = <&ccache>;
75 reg = <0x2>;
77 tlb-split;
78 cpu2_intc: interrupt-controller {
79 compatible = "riscv,cpu-intc";
80 #interrupt-cells = <1>;
81 interrupt-controller;
88 d-cache-block-size = <64>;
89 d-cache-sets = <64>;
90 d-cache-size = <32768>;
91 d-tlb-sets = <1>;
92 d-tlb-size = <40>;
93 i-cache-block-size = <64>;
94 i-cache-sets = <64>;
95 i-cache-size = <32768>;
96 i-tlb-sets = <1>;
97 i-tlb-size = <40>;
98 mmu-type = "riscv,sv39";
99 next-level-cache = <&ccache>;
100 reg = <0x3>;
102 tlb-split;
103 cpu3_intc: interrupt-controller {
104 compatible = "riscv,cpu-intc";
105 #interrupt-cells = <1>;
106 interrupt-controller;
113 d-cache-block-size = <64>;
114 d-cache-sets = <64>;
115 d-cache-size = <32768>;
116 d-tlb-sets = <1>;
117 d-tlb-size = <40>;
118 i-cache-block-size = <64>;
119 i-cache-sets = <64>;
120 i-cache-size = <32768>;
121 i-tlb-sets = <1>;
122 i-tlb-size = <40>;
123 mmu-type = "riscv,sv39";
124 next-level-cache = <&ccache>;
125 reg = <0x4>;
127 tlb-split;
128 cpu4_intc: interrupt-controller {
129 compatible = "riscv,cpu-intc";
130 #interrupt-cells = <1>;
131 interrupt-controller;
138 reg = <0x0 0x8000000 0x0 0x200000>;
142 #address-cells = <2>;
143 #size-cells = <2>;
144 #clock-cells = <1>;
145 compatible = "starfive,jh7110", "simple-bus";
149 compatible = "starfive,jh7110-clint", "sifive,clint0";
150 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
155 reg = <0x0 0x2000000 0x0 0x10000>;
158 ccache: cache-controller@2010000 {
159 cache-block-size = <64>;
160 cache-level = <2>;
161 cache-sets = <2048>;
162 cache-size = <2097152>;
163 cache-unified;
164 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
165 interrupt-parent = <&plic>;
167 reg = <0x0 0x2010000 0x0 0x4000>;
170 plic: interrupt-controller@c000000 {
171 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
172 #address-cells = <0>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 interrupts-extended = <&cpu0_intc 11>,
180 reg = <0x0 0x0c000000 0x0 0x04000000>;
181 riscv,max-priority = <7>;
186 compatible = "ns16550", "snps,dw-apb-uart";
188 clock-names = "baudclk", "apb_pclk";
189 clock-frequency = <100000000>;
190 current-speed = <115200>;
191 interrupt-parent = <&plic>;
193 reg = <0x0 0x10000000 0x0 0x10000>;
194 reg-shift = <2>;
199 compatible = "ns16550", "snps,dw-apb-uart";
201 clock-names = "baudclk", "apb_pclk";
202 clock-frequency = <100000000>;
203 current-speed = <115200>;
204 interrupt-parent = <&plic>;
206 reg = <0x0 0x10010000 0x0 0x10000>;
207 reg-shift = <2>;