Searched refs:interrupts (Results 1 – 25 of 25) sorted by relevance
| /Renode-v1.15.3-c57714d/tests/platforms/systemc/interrupts/ |
| D | interrupts.robot | 2 … @https://dl.antmicro.com/projects/renode/systemc-examples-zephyr-interrupts-stm32f401_mini.e…
3 … @https://dl.antmicro.com/projects/renode/x64-systemc--interrupts.elf-s_1017672-89…
4 ${PLATFORM} @tests/platforms/systemc/interrupts/interrupts.repl
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| /Renode-v1.15.3-c57714d/src/Plugins/CoSimulationPlugin/IntegrationLibrary/src/ |
| D | renode_bus.cpp | 170 interrupts.push_back({irq, 0, irq_addr}); in registerInterrupt()
175 for (unsigned long i = 0; i < interrupts.size(); i++) { in handleInterrupts()
176 if (*interrupts[i].irq != interrupts[i].prev_irq) { in handleInterrupts()
177 … communicationChannel->sendSender(Protocol(interrupt, interrupts[i].irq_addr, *interrupts[i].irq)); in handleInterrupts()
178 interrupts[i].prev_irq = *interrupts[i].irq; in handleInterrupts()
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| D | renode_bus.h | 71 std::vector<Interrupt> interrupts; variable
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| /Renode-v1.15.3-c57714d/tests/peripherals/CLIC/ |
| D | CLIC-priorities-01.robot | 27 # Trigger the three interrupts.
33 # This forces CLIC to prioritize the interrupts.
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| D | CLIC-level-prio-01.robot | 27 …# Trigger interrupts 17 and 18; they have the same level, but 17 has a higher priority so it shoul…
32 # This forces CLIC to prioritize the interrupts.
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| /Renode-v1.15.3-c57714d/scripts/single-node/ |
| D | murax.resc | 19 # this is a hack to allow handling interrupts at all; this should be after #13326
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| D | murax_verilated_uart.resc | 29 # this is a hack to allow handling interrupts at all; this should be after #13326
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| /Renode-v1.15.3-c57714d/tests/platforms/MiV/ |
| D | MiV.robot | 80 …# it is related to a bug in LiteOS (stack overflow and corruption) when interrupts happens in *wro…
107 …Create Machine riscv-interrupt-blinky_gpio-interrupts-edge-positive.elf-s_135192-436f26…
135 …Create Machine riscv-interrupt-blinky_gpio-interrupts-edge-negative.elf-s_135192-19e453…
160 …Create Machine riscv-interrupt-blinky_gpio-interrupts-edge-both.elf-s_135192-1afc01350e…
186 …Create Machine riscv-interrupt-blinky_gpio-interrupts-level-high.elf-s_135168-e03e81b69…
224 …Create Machine riscv-interrupt-blinky_gpio-interrupts-level-low.elf-s_135168-f570dad79e…
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| /Renode-v1.15.3-c57714d/tests/platforms/ |
| D | Icicle-Kit.robot | 47 [Tags] linux uart interrupts
62 [Tags] linux uart interrupts
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| D | QuarkC1000.robot | 20 [Tags] zephyr uart interrupts
49 [Tags] zephyr uart interrupts
66 [Tags] zephyr uart interrupts gpio button non_critical
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| D | Murax.robot | 9 # this is a hack to allow handling interrupts at all; this should be fixed after #13326
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| D | SiFive-FU540.robot | 25 [Tags] linux uart interrupts
42 [Tags] linux uart interrupts
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| D | Zedboard.robot | 549 # Enable all interrupts
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| /Renode-v1.15.3-c57714d/tests/platforms/SiFive-FE310/ |
| D | SiFive-FE310.robot | 10 [Tags] zephyr uart interrupts
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| /Renode-v1.15.3-c57714d/platforms/cpus/ |
| D | sam_e70.repl | 38 // our model does not support interrupts yet, but if it did:
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| D | sifive-fu740.repl | 69 // our model does not support interrupts yet, but if it did:
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| D | sifive-fu540.repl | 111 // our model does not support interrupts yet, but if it did:
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| D | stm32l552.repl | 18 // it is currently here to support direct interrupts
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| D | stm32g0.repl | 17 // it is currently here to support direct interrupts
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| D | polarfire-soc.repl | 65 // No user mode or hypervisor mode interrupts
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| /Renode-v1.15.3-c57714d/tests/platforms/verilated/ |
| D | MuraxAPB3.robot | 53 # this is a hack to allow handling interrupts at all; this should be fixed after #13326
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| /Renode-v1.15.3-c57714d/platforms/cpus/silabs/efr32s2/ |
| D | efr32mg24.repl | 67 // Main CPU interrupts
78 // Sequencer CPU interrupts
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| D | efr32mg26.repl | 67 // Main CPU interrupts
78 // Sequencer CPU interrupts
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| /Renode-v1.15.3-c57714d/ |
| D | CHANGELOG.rst | 272 * timer interrupts configuration for STM32F4-based platforms
490 * NXP LPC2294 SoC with UART, CAN, timer and interrupts support
654 * support for NMI interrupts in RISC-V
1234 * add debug mode for all architectures disabling interrupts when stepping over guest code
1238 * added interrupts support in verilated peripherals
1598 * VexRiscv now supports Supervisor level interrupts, following latest changes to this core
1603 * VerilatedUART now supports interrupts
1641 * vectored interrupts support in RISC-V
1729 * crash when completing interrupts in PLIC when no interrupt is pending
1775 * local interrupts in PolarFire SoC platform
[all …]
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| /Renode-v1.15.3-c57714d/tests/unit-tests/ |
| D | big-endian-watchpoint.robot | 192 Wait For Log Entry CPU abort [PC=0x14]: Trap 0x02 while interrupts disabled timeout=1
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