1e51: CPU.RiscV64 @ sysbus
2    cpuType: "rv64imac_zicsr_zifencei"
3    hartId: 0
4    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
5    timeProvider: clint
6
7u54_1: CPU.RiscV64 @ sysbus
8    cpuType: "rv64gc_zicsr_zifencei"
9    hartId: 1
10    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
11    timeProvider: clint
12
13u54_2: CPU.RiscV64 @ sysbus
14    cpuType: "rv64gc_zicsr_zifencei"
15    hartId: 2
16    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
17    timeProvider: clint
18
19u54_3: CPU.RiscV64 @ sysbus
20    cpuType: "rv64gc_zicsr_zifencei"
21    hartId: 3
22    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
23    timeProvider: clint
24
25u54_4: CPU.RiscV64 @ sysbus
26    cpuType: "rv64gc_zicsr_zifencei"
27    hartId: 4
28    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
29    timeProvider: clint
30
31debug: Memory.MappedMemory @sysbus 0x0
32    size: 0x1000
33
34e51DTim: Memory.MappedMemory @ sysbus 0x01000000
35    size: 0x2000
36
37u54Hart1ITim: Memory.MappedMemory @ sysbus 0x01808000
38    size: 0x7000
39
40u54Hart2ITim: Memory.MappedMemory @ sysbus 0x01810000
41    size: 0x7000
42
43u54Hart3ITim: Memory.MappedMemory @ sysbus 0x01818000
44    size: 0x7000
45
46u54Hart4ITim: Memory.MappedMemory @ sysbus 0x01820000
47    size: 0x7000
48
49clint: IRQControllers.CoreLevelInterruptor  @ sysbus 0x2000000
50    frequency: 1000000
51    numberOfTargets: 5
52    [0, 1] -> e51@[3, 7]
53    [2, 3] -> u54_1@[3, 7]
54    [4, 5] -> u54_2@[3, 7]
55    [6, 7] -> u54_3@[3, 7]
56    [8, 9] -> u54_4@[3, 7]
57
58plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0xc000000
59    0 -> e51@11
60    [1,2] -> u54_1@[11,9]
61    [3,4] -> u54_2@[11,9]
62    [5,6] -> u54_3@[11,9]
63    [7,8] -> u54_4@[11,9]
64    numberOfSources: 53
65    numberOfContexts: 9
66    prioritiesEnabled : false
67
68uart0: UART.SiFive_UART @ sysbus 0x10010000
69    IRQ -> plic@4
70
71uart1: UART.SiFive_UART @ sysbus 0x10011000
72    IRQ -> plic@5
73
74gpio: GPIOPort.SiFive_GPIO @ sysbus 0x10060000
75
76qspi0Flash: Memory.MappedMemory @ sysbus 0x20000000
77    size: 0x2000000
78
79ddr: Memory.MappedMemory @ sysbus 0x80000000
80    size: 0x200000000
81
82ethernet: Network.CadenceGEM @ sysbus 0x10090000
83    moduleRevision: 0x0109
84    moduleId: 0x1007
85    IRQ -> plic@53
86
87phy: Network.EthernetPhysicalLayer @ ethernet 0
88    Id1: 0x0141
89    Id2: 0x0e40
90    BasicStatus: 0x62A4
91    AutoNegotiationAdvertisement: 0x1e1
92    AutoNegotiationLinkPartnerBasePageAbility: 0x1e1
93    MasterSlaveControl: 0x300
94    MasterSlaveStatus: 0x3000
95
96qspi0: SPI.HiFive_SPI @ sysbus 0x10040000
97    IRQ -> plic@51
98    numberOfSupportedSlaves: 1
99
100// The registration address value is taken from the device tree.
101// It is different in the documentation (0x10140000).
102qspi1: SPI.HiFive_SPI @ sysbus 0x10041000
103    IRQ -> plic@52
104    numberOfSupportedSlaves: 4
105
106qspi2: SPI.HiFive_SPI @ sysbus 0x10050000
107    IRQ -> plic@6
108    numberOfSupportedSlaves: 1
109
110i2c: I2C.OpenCoresI2C @ sysbus 0x10030000
111    // our model does not support interrupts yet, but if it did:
112    // IRQ -> plic@50
113
114pwm0: HiFive_PWM @ sysbus 0x10020000
115    IRQ -> plic@42
116
117pwm1: HiFive_PWM @ sysbus 0x10021000
118    IRQ -> plic@46
119
120