1e51: CPU.RiscV64 @ sysbus
2    cpuType: "rv64imac_zicsr_zifencei"
3    hartId: 0
4    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
5    timeProvider: clint
6    CyclesPerInstruction: 8
7    init:
8        RegisterCustomCSR "BPM" 0x7C0 Machine
9
10u54_1: CPU.RiscV64 @ sysbus
11    cpuType: "rv64gc_zicsr_zifencei"
12    hartId: 1
13    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
14    timeProvider: clint
15    CyclesPerInstruction: 8
16    allowUnalignedAccesses: true
17    init:
18        RegisterCustomCSR "BPM" 0x7C0 Machine
19
20u54_2: CPU.RiscV64 @ sysbus
21    cpuType: "rv64gc_zicsr_zifencei"
22    hartId: 2
23    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
24    timeProvider: clint
25    CyclesPerInstruction: 8
26    allowUnalignedAccesses: true
27    init:
28        RegisterCustomCSR "BPM" 0x7C0 Machine
29
30u54_3: CPU.RiscV64 @ sysbus
31    cpuType: "rv64gc_zicsr_zifencei"
32    hartId: 3
33    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
34    timeProvider: clint
35    CyclesPerInstruction: 8
36    allowUnalignedAccesses: true
37    init:
38        RegisterCustomCSR "BPM" 0x7C0 Machine
39
40u54_4: CPU.RiscV64 @ sysbus
41    cpuType: "rv64gc_zicsr_zifencei"
42    hartId: 4
43    privilegedArchitecture: PrivilegedArchitecture.Priv1_10
44    timeProvider: clint
45    CyclesPerInstruction: 8
46    allowUnalignedAccesses: true
47    init:
48        RegisterCustomCSR "BPM" 0x7C0 Machine
49
50clint: IRQControllers.CoreLevelInterruptor  @ sysbus 0x2000000
51    frequency: 1000000
52    numberOfTargets: 5
53    [0, 1] -> e51@[3, 7]
54    [2, 3] -> u54_1@[3, 7]
55    [4, 5] -> u54_2@[3, 7]
56    [6, 7] -> u54_3@[3, 7]
57    [8, 9] -> u54_4@[3, 7]
58
59pdma: DMA.MPFS_PDMA @ sysbus 0x3000000
60    [0-7] -> plic@[5-12]
61
62plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0xc000000
63    // E51: only machine mode interrupt
64    0 -> e51@11
65    // No user mode or hypervisor mode interrupts
66    [1,2] -> u54_1@[11,9]
67    [3,4] -> u54_2@[11,9]
68    [5,6] -> u54_3@[11,9]
69    [7,8] -> u54_4@[11,9]
70    numberOfSources: 186
71    numberOfContexts: 9
72    prioritiesEnabled : false
73
74mmuart0: UART.NS16550 @ sysbus 0x20000000
75    wideRegisters: true
76    IRQ -> plic@90 | e51@27
77
78mmuart1: UART.NS16550 @ sysbus 0x20100000
79    wideRegisters: true
80    IRQ -> plic@91 | u54_1@27
81
82mmuart2: UART.NS16550 @ sysbus 0x20102000
83    wideRegisters: true
84    IRQ -> plic@92 | u54_2@27
85
86mmuart3: UART.NS16550 @ sysbus 0x20104000
87    wideRegisters: true
88    IRQ -> plic@93 | u54_3@27
89
90mmuart4: UART.NS16550 @ sysbus 0x20106000
91    wideRegisters: true
92    IRQ -> plic@94 | u54_4@27
93
94mmc: SD.MPFS_SDController @ sysbus 0x20008000
95    IRQ -> plic@88
96    WakeupIRQ -> plic@89
97
98spi0: SPI.MPFS_SPI @ sysbus 0x20108000
99    IRQ -> plic@54
100
101spi1: SPI.MPFS_SPI @ sysbus 0x20109000
102    IRQ -> plic@55
103
104i2c0: I2C.MPFS_I2C @ sysbus 0x2010A000
105    IRQ -> plic@58
106
107i2c1: I2C.MPFS_I2C @ sysbus 0x2010B000
108    IRQ -> plic@61
109
110can0: CAN.MPFS_CAN @ sysbus 0x2010C000
111    IRQ -> plic@56
112
113can1: CAN.MPFS_CAN @ sysbus 0x2010D000
114    IRQ -> plic@57
115
116mac0: Network.CadenceGEM @ { sysbus 0x20110000; sysbus 0x28110000 }
117    IRQ -> plic@64 | u54_1@24 | u54_2@24
118
119mac1: Network.CadenceGEM @ { sysbus 0x20112000; sysbus 0x28112000 }
120    IRQ -> plic@70 | u54_3@24 | u54_4@24
121
122phy: Network.EthernetPhysicalLayer @ {
123        // this is a slight hack to enable testing on multiple physical configurations with a single repl
124        mac0 3;
125        mac0 4;
126        mac0 16;
127        mac1 3;
128        mac1 4;
129        mac1 9;
130        mac1 16
131    }
132    BasicStatus: 0x62A4
133    Id1: 0x0007
134    Id2: 0x0660
135    AutoNegotiationAdvertisement: 0x1e1
136    AutoNegotiationLinkPartnerBasePageAbility: 0x1e1
137    MasterSlaveControl: 0x300
138    MasterSlaveStatus: 0x3000
139
140gpio0: GPIOPort.MPFS_GPIO @ sysbus 0x20120000
141    [0-13] -> plic@[13-26]
142    IRQ -> plic@51
143
144gpio1: GPIOPort.MPFS_GPIO @ sysbus 0x20121000
145    [0-23] -> plic@[27-50]
146    IRQ -> plic@52
147
148gpio2: GPIOPort.MPFS_GPIO @ sysbus 0x20122000
149    [0-31] -> plic@[13-44]
150    IRQ -> plic@53
151
152wdog0: Timers.MPFS_Watchdog @ sysbus 0x20001000
153    frequency: 156250 //this value is estimated from the comments in the code
154    RefreshEnable -> plic@100 | e51@26
155    Trigger -> plic@105 | e51@25
156
157wdog1: Timers.MPFS_Watchdog @ sysbus 0x20101000
158    frequency: 156250 //this value is estimated from the comments in the code
159    RefreshEnable -> plic@101 | u54_1@26
160    Trigger -> plic@106 | u54_1@25 | e51@24
161
162wdog2: Timers.MPFS_Watchdog @ sysbus 0x20103000
163    frequency: 156250 //this value is estimated from the comments in the code
164    RefreshEnable -> plic@102 | u54_2@26
165    Trigger -> plic@107 | u54_2@25 | e51@23
166
167wdog3: Timers.MPFS_Watchdog @ sysbus 0x20105000
168    frequency: 156250 //this value is estimated from the comments in the code
169    RefreshEnable -> plic@103 | u54_3@26
170    Trigger -> plic@108 | u54_3@25 | e51@22
171
172wdog4: Timers.MPFS_Watchdog @ sysbus 0x20107000
173    frequency: 156250 //this value is estimated from the comments in the code
174    RefreshEnable -> plic@104 | u54_4@26
175    Trigger -> plic@109 | u54_4@25 | e51@21
176
177rtc: Timers.MPFS_RTC @ sysbus 0x20124000
178    WakeupIRQ -> plic@80
179    MatchIRQ -> plic@81
180
181mstimer: Timers.MPFS_Timer @ sysbus 0x20125000
182    Timer1IRQ -> plic@82
183    Timer2IRQ -> plic@83
184
185envmCfg: MTD.MPFS_eNVM @ sysbus 0x20200000
186    memory: envmData
187    IRQ -> plic@84
188
189envmData: Memory.MappedMemory @ sysbus 0x20220000
190    size: 0x20000
191
192usb: USB.MPFS_USB @ sysbus 0x20201000
193    DmaIRQ -> plic@86
194    MainIRQ -> plic@87
195
196l2Lim: Memory.MappedMemory @ sysbus 0x08000000
197    size: 0x02000000
198
199l2ZeroDevice: Memory.MappedMemory @ sysbus 0x0A000000
200    size: 0x02000000
201
202e51DTim: Memory.MappedMemory @ sysbus 0x01000000
203    size: 0x2000
204
205e51Hart0ITim: Memory.MappedMemory @ sysbus 0x01800000
206    size: 0x2000
207
208u54Hart1ITim: Memory.MappedMemory @ sysbus 0x01808000
209    size: 0x7000
210
211u54Hart2ITim: Memory.MappedMemory @ sysbus 0x01810000
212    size: 0x7000
213
214u54Hart3ITim: Memory.MappedMemory @ sysbus 0x01818000
215    size: 0x7000
216
217u54Hart4ITim: Memory.MappedMemory @ sysbus 0x01820000
218    size: 0x7000
219
220// The exact DDR Memory Partition depends on the amount of physically connected DDR memory.
221// Both BeagleV-Fire and PolarFire SoC Icicle Kit based on this soc are equipped with 2GB,
222// so we put it here divided into ddr and ddr2 parts as a sane default.
223// Override size at a board level if different configuration is expected.
224ddr: Memory.MappedMemory @ {
225        sysbus 0x80000000;
226        sysbus <0xC0000000, +0x10000000>;
227        sysbus <0xD0000000, +0x10000000>;
228        sysbus 0x1000000000;
229        sysbus 0x1400000000;
230        sysbus 0x1800000000
231    }
232    size: 0x40000000
233
234ddr2: Memory.MappedMemory @ {
235        sysbus 0x1040000000;
236        sysbus 0x1440000000;
237        sysbus 0x1840000000
238    }
239    size: 0x40000000
240
241mem_bootloader: Memory.MappedMemory @ sysbus 0x0
242    size: 0x100000
243
244pcie0: PCI.MPFS_PCIe @ sysbus 0x53004000
245
246pcie1: PCI.MPFS_PCIe @ {
247        sysbus 0x53008000;
248        sysbus new Bus.BusMultiRegistration { address: 0x60000000; size: 0x20000000; region: "ecam" }
249    }
250
251pcieRC0: PCI.PCIeRootComplex @ pcie0 0
252    parent: pcie1
253
254pcieRC1: PCI.PCIeRootComplex @ pcie1 0
255    parent: pcie1
256
257pcieMem: PCI.PCIeMemory  @ pcie1 1
258    size: 0x20000
259    parent: pcie1
260
261mailbox: Memory.ArrayMemory @ sysbus 0x37020800
262    size: 0x800
263
264athena: Miscellaneous.Crypto.AthenaX5200 @ sysbus 0x22000000
265
266ioscb: Python.PythonPeripheral @ sysbus 0x37080000
267    size: 0x1f7ffff
268    script: '''request.value = 0xFFFFFFFF'''
269
270// There are 8 BootRom registers covering range from 0x20003120 to 0x2000313F,
271// but because of Renode's memory alignment limitations they are mapped as a single memory
272sysregScbBootRom: Memory.MappedMemory @ sysbus 0x20003000
273    size: 0x1000
274
275DDR_CTRLR: Miscellaneous.MPFS_DDRMock @ sysbus 0x3e001000
276DDR_PHY: Miscellaneous.MPFS_DDRMock @ sysbus 0x20007000
277SCB_DDR_PLL: Miscellaneous.MPFS_DDRMock @ sysbus 0x3e010000
278DDRCFG: Miscellaneous.MPFS_DDRMock @ sysbus 0x20080000
279
280CacheConfig_WayEnable: Python.PythonPeripheral @ sysbus 0x02010008
281    size: 0x8
282    initable: true
283    script: '''
284if request.isInit:
285    reg = 0x0
286elif request.isRead:
287    request.value = reg
288elif request.isWrite:
289    reg = request.value
290'''
291
292TopSystemRegisters: Miscellaneous.MPFS_Sysreg @ sysbus 0x20002000
293
294sysbus:
295    init:
296        // DDR Memory Address Space is tagged below.
297        // The exact DDR Memory Partition depends on the amount of physically connected DDR memory.
298        Tag <0x80000000 0x40000000> "DDR Cached 1GB"
299        Tag <0x1000000000 0x400000000> "DDR Cached 16GB"
300        Tag <0xC0000000 0x10000000> "DDR Non-Cached 256MB"
301        Tag <0xD0000000 0x10000000> "DDR Non-Cached WCB 256MB"
302        Tag <0x1400000000 0x400000000> "DDR Non-Cached 16GB"
303        Tag <0x1800000000 0x400000000> "DDR Non-Cached WCB 16GB"
304        SilenceRange <0x02010010, 0x02010FFF> # "Cache controller"
305        SilenceRange <0x01700000, 0x01704FFF> # Bus error units
306        Tag <0x37080000, 0x38FFFFFF> "IOSCB" 0xFFFFFFFF
307        Tag <0x20005000, 0x20005FFF> "MPU Config"
308
309        Tag <0x20007000, 0x20007FFF> "CFG_DDR_SGMII_PHY"
310        Tag <0x20007208, 0x2000720B> "IOC_REG1" 0xFF
311        Tag <0x20007814, 0x20007817> "TRAINING_STATUS" 0xFF
312        Tag <0x20007808, 0x2000780B> "LANE_SELECT" 0
313        Tag <0x2000781C, 0x2000781F> "GT_ERR_COMB" 0
314        Tag <0x20007834, 0x20007837> "DQ_DQS_ERR_DONE" 0x8
315        Tag <0x2000784C, 0x2000784F> "DQDQS_WINDOW" 0x8
316        Tag <0x20007C20, 0x20007C23> "PVT_STAT" 0x4040
317
318        Tag <0x20080000, 0x2009FFFF> "DDRCFG"
319        Tag <0x20084428, 0x2008442B> "CSR_APB_MT_DONE_ACK" 0x1
320        Tag <0x20090034, 0x20090037> "CSR_APB_STAT_DFI_INIT_COMPLETE" 0x1
321        Tag <0x20090038, 0x2009003B> "CSR_APB_STAT_DFI_TRAINING_COMPLETE" 0x1
322        Tag <0x3E040008, 0x3E04000B> "IOSCB_IO_CALIB_DDR:IOC_REG1" 0xFF
323