| /Linux-v5.10/arch/sparc/kernel/ |
| D | iommu.c | 2 /* iommu.c: Generic sparc64 IOMMU support.
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
49 /* Must be invoked under the IOMMU lock. */
52 struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl); in iommu_flushall() local
53 if (iommu->iommu_flushinv) { in iommu_flushall()
54 iommu_write(iommu->iommu_flushinv, ~(u64)0); in iommu_flushall()
59 tag = iommu->iommu_tags; in iommu_flushall()
66 (void) iommu_read(iommu->write_complete_reg); in iommu_flushall()
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| D | iommu-common.c | 3 * IOMMU mmap management and range allocation functions.
4 * Based almost entirely upon the powerpc iommu allocator.
10 #include <linux/iommu-helper.h>
13 #include <asm/iommu-common.h>
19 static inline bool need_flush(struct iommu_map_table *iommu) in need_flush() argument
21 return ((iommu->flags & IOMMU_NEED_FLUSH) != 0); in need_flush()
24 static inline void set_flush(struct iommu_map_table *iommu) in set_flush() argument
26 iommu->flags |= IOMMU_NEED_FLUSH; in set_flush()
29 static inline void clear_flush(struct iommu_map_table *iommu) in clear_flush() argument
31 iommu->flags &= ~IOMMU_NEED_FLUSH; in clear_flush()
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| /Linux-v5.10/drivers/iommu/ |
| D | sun50i-iommu.c | 10 #include <linux/dma-iommu.h>
15 #include <linux/iommu.h>
97 struct iommu_device iommu; member
99 /* Lock to modify the IOMMU registers */
122 struct sun50i_iommu *iommu; member
135 static u32 iommu_read(struct sun50i_iommu *iommu, u32 offset) in iommu_read() argument
137 return readl(iommu->base + offset); in iommu_read()
140 static void iommu_write(struct sun50i_iommu *iommu, u32 offset, u32 value) in iommu_write() argument
142 writel(value, iommu->base + offset); in iommu_write()
146 * The Allwinner H6 IOMMU uses a 2-level page table.
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| D | msm_iommu.c | 18 #include <linux/iommu.h>
55 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
59 ret = clk_enable(iommu->pclk); in __enable_clocks()
63 if (iommu->clk) { in __enable_clocks()
64 ret = clk_enable(iommu->clk); in __enable_clocks()
66 clk_disable(iommu->pclk); in __enable_clocks()
72 static void __disable_clocks(struct msm_iommu_dev *iommu) in __disable_clocks() argument
74 if (iommu->clk) in __disable_clocks()
75 clk_disable(iommu->clk); in __disable_clocks()
76 clk_disable(iommu->pclk); in __disable_clocks()
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| D | rockchip-iommu.c | 3 * IOMMU API for Rockchip
13 #include <linux/dma-iommu.h>
18 #include <linux/iommu.h>
94 /* list of clocks required by IOMMU */
107 struct iommu_device iommu; member
109 struct iommu_domain *domain; /* domain to which iommu is attached */
114 struct device_link *link; /* runtime PM link from IOMMU to master */
115 struct rk_iommu *iommu; member
134 * The Rockchip rk3288 iommu uses a 2-level page table.
143 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
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| D | iommu-sysfs.c | 3 * IOMMU sysfs class support
10 #include <linux/iommu.h>
16 * As devices are added to the IOMMU, we'll add links to the group.
38 .name = "iommu",
50 * Init the struct device for the IOMMU. IOMMU specific attributes can
52 * IOMMU type.
54 int iommu_device_sysfs_add(struct iommu_device *iommu, in iommu_device_sysfs_add() argument
62 iommu->dev = kzalloc(sizeof(*iommu->dev), GFP_KERNEL); in iommu_device_sysfs_add()
63 if (!iommu->dev) in iommu_device_sysfs_add()
66 device_initialize(iommu->dev); in iommu_device_sysfs_add()
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| D | Kconfig | 15 bool "IOMMU Hardware Support"
26 menu "Generic IOMMU Pagetable Support"
59 for 64KB pages/16MB supersections if indicated by the IOMMU driver.
73 bool "Export IOMMU internals in DebugFS"
76 Allows exposure of IOMMU device internals. This option enables
77 the use of debugfs by IOMMU drivers as required. Devices can,
78 at initialization time, cause the IOMMU code to create a top-level
79 debug/iommu directory, and then populate a subdirectory with
83 bool "IOMMU passthrough by default"
87 iommu.passthrough=on or iommu=pt through command line. If this
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| /Linux-v5.10/Documentation/devicetree/bindings/pci/ |
| D | pci-iommu.txt | 2 relationship between PCI(e) devices and IOMMU(s).
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
39 (rid-base,iommu,iommu-base,length).
42 the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
44 - iommu-map-mask: A mask to be applied to each Requester ID prior to being
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| /Linux-v5.10/drivers/iommu/amd/ |
| D | init.c | 19 #include <linux/amd-iommu.h>
24 #include <asm/iommu.h>
97 * structure describing one IOMMU in the ACPI table. Typically followed by one
117 * A device entry describing which devices a specific IOMMU translates and
133 * An AMD IOMMU memory definition structure. It defines things like exclusion
198 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
204 * The rlookup table is used to find the IOMMU which is responsible
217 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
260 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
262 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
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| /Linux-v5.10/Documentation/devicetree/bindings/iommu/ |
| D | iommu.txt | 5 IOMMU device node:
8 An IOMMU can provide the following services:
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
36 1:1 mapping from IOMMU to memory.
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
43 The meaning of the IOMMU specifier is defined by the device tree binding of
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| D | qcom,iommu.txt | 1 * QCOM IOMMU v1 Implementation
4 a similar looking IOMMU but without access to the global register space,
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
27 - #iommu-cells : Must be 1. Index identifies the context-bank #.
29 - ranges : Base address and size of the iommu context banks.
31 - qcom,iommu-secure-id : secure-id.
37 - "qcom,msm-iommu-v1-ns" : non-secure context bank
38 - "qcom,msm-iommu-v1-sec" : secure context bank
39 - reg : Base address and size of context bank within the iommu
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| D | ti,omap-iommu.txt | 1 OMAP2+ IOMMU
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
16 Documentation/devicetree/bindings/iommu/iommu.txt
21 - ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
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| D | msm,iommu-v0.txt | 1 * QCOM IOMMU
3 The MSM IOMMU is an implementation compatible with the ARM VMSA short
5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
27 required for iommu's register accesses.
29 required by iommu for bus accesses.
31 Each bus master connected to an IOMMU must reference the IOMMU in its device
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| /Linux-v5.10/drivers/iommu/intel/ |
| D | irq_remapping.c | 13 #include <linux/intel-iommu.h>
33 struct intel_iommu *iommu; member
40 struct intel_iommu *iommu; member
47 struct intel_iommu *iommu; member
74 * ->iommu->register_lock
83 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
86 static bool ir_pre_enabled(struct intel_iommu *iommu) in ir_pre_enabled() argument
88 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); in ir_pre_enabled()
91 static void clear_ir_pre_enabled(struct intel_iommu *iommu) in clear_ir_pre_enabled() argument
93 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED; in clear_ir_pre_enabled()
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| D | iommu.c | 33 #include <linux/iommu.h>
34 #include <linux/intel-iommu.h>
47 #include <asm/iommu.h>
90 * to the IOMMU core, which will then use this information to split
94 * Traditionally the IOMMU core just handed us the mappings directly,
101 * If at some point we'd like to utilize the IOMMU core's new behavior,
171 /* global iommu list, set NULL for ignored DMAR units */
293 * 2. It maps to each iommu if successful.
294 * 3. Each iommu mapps to this domain if successful.
414 static bool translation_pre_enabled(struct intel_iommu *iommu) in translation_pre_enabled() argument
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| D | dmar.c | 22 #include <linux/intel-iommu.h>
29 #include <linux/iommu.h>
65 static void free_iommu(struct intel_iommu *iommu);
462 if (dmaru->iommu) in dmar_free_drhd()
463 free_iommu(dmaru->iommu); in dmar_free_drhd()
502 drhd->iommu->node = node; in dmar_parse_one_rhsa()
761 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", in dmar_acpi_insert_dev_scope()
932 x86_init.iommu.iommu_init = intel_iommu_init; in detect_intel_iommu()
947 static void unmap_iommu(struct intel_iommu *iommu) in unmap_iommu() argument
949 iounmap(iommu->reg); in unmap_iommu()
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| D | pasid.c | 15 #include <linux/intel-iommu.h>
16 #include <linux/iommu.h>
25 * Intel IOMMU system wide PASID name space:
30 int vcmd_alloc_pasid(struct intel_iommu *iommu, u32 *pasid) in vcmd_alloc_pasid() argument
37 raw_spin_lock_irqsave(&iommu->register_lock, flags); in vcmd_alloc_pasid()
38 dmar_writeq(iommu->reg + DMAR_VCMD_REG, VCMD_CMD_ALLOC); in vcmd_alloc_pasid()
39 IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq, in vcmd_alloc_pasid()
41 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in vcmd_alloc_pasid()
49 pr_info("IOMMU: %s: No PASID available\n", iommu->name); in vcmd_alloc_pasid()
54 pr_warn("IOMMU: %s: Unexpected error code %d\n", in vcmd_alloc_pasid()
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| D | debugfs.c | 13 #include <linux/intel-iommu.h>
113 struct intel_iommu *iommu; in iommu_regset_show() local
119 for_each_active_iommu(iommu, drhd) { in iommu_regset_show()
121 seq_puts(m, "IOMMU: Invalid base address\n"); in iommu_regset_show()
126 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n", in iommu_regset_show()
127 iommu->name, drhd->reg_base_addr); in iommu_regset_show()
133 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_regset_show()
135 value = dmar_readl(iommu->reg + iommu_regs_32[i].offset); in iommu_regset_show()
141 value = dmar_readq(iommu->reg + iommu_regs_64[i].offset); in iommu_regset_show()
146 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_regset_show()
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| /Linux-v5.10/Documentation/devicetree/bindings/virtio/ |
| D | iommu.txt | 1 * virtio IOMMU PCI device
3 When virtio-iommu uses the PCI transport, its programming interface is
5 device tree statically describes the relation between IOMMU and DMA
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
7 contains a child node representing the IOMMU device explicitly.
11 - compatible: Should be "virtio,pci-iommu"
12 - reg: PCI address of the IOMMU. As defined in the PCI Bus
18 - #iommu-cells: Each platform DMA master managed by the IOMMU is assigned
20 For virtio-iommu, #iommu-cells must be 1.
24 - DMA from the IOMMU device isn't managed by another IOMMU. Therefore the
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| D | mmio.txt | 11 Required properties for virtio-iommu:
13 - #iommu-cells: When the node corresponds to a virtio-iommu device, it is
14 linked to DMA masters using the "iommus" or "iommu-map"
15 properties [1][2]. #iommu-cells specifies the size of the
16 "iommus" property. For virtio-iommu #iommu-cells must be
21 - iommus: If the device accesses memory through an IOMMU, it should
22 have an "iommus" property [1]. Since virtio-iommu itself
23 does not access memory through an IOMMU, the "virtio,mmio"
24 node cannot have both an "#iommu-cells" and an "iommus"
38 viommu: iommu@3100 {
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| /Linux-v5.10/arch/powerpc/platforms/cell/ |
| D | iommu.c | 3 * IOMMU implementation for Cell Broadband Processor Architecture
22 #include <asm/iommu.h>
93 /* IOMMU sizing */
102 struct cbe_iommu *iommu; member
129 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, in invalidate_tce_cache() argument
136 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; in invalidate_tce_cache()
193 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_build_cell()
216 __pa(window->iommu->pad_page) | in tce_free_cell()
227 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_free_cell()
233 struct cbe_iommu *iommu = data; in ioc_interrupt() local
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| /Linux-v5.10/drivers/vfio/ |
| D | vfio_iommu_type1.c | 3 * VFIO: IOMMU DMA mapping support for Type1 IOMMU
12 * We arbitrarily define a Type1 IOMMU as one matching the below code.
13 * It could be called the x86 IOMMU as it's designed for AMD-Vi & Intel
15 * implementing a similar IOMMU could make use of this. We expect the
16 * IOMMU to support the IOMMU API and have few to no restrictions around
17 * the IOVA range that can be mapped. The Type1 IOMMU is currently
19 * userpsace pages pinned into memory. We also assume devices and IOMMU
20 * domains are PCI based as the IOMMU API is still centered around a
27 #include <linux/iommu.h>
40 #include <linux/dma-iommu.h>
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| /Linux-v5.10/Documentation/devicetree/bindings/media/ |
| D | mediatek-vcodec.txt | 20 - iommus : should point to the respective IOMMU block with master port as
21 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
46 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
47 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
48 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
49 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
50 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
51 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
52 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
53 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
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| /Linux-v5.10/arch/sparc/mm/ |
| D | iommu.c | 3 * iommu.c: IOMMU specific routines for memory management.
25 #include <asm/iommu.h>
59 struct iommu_struct *iommu; in sbus_iommu_init() local
66 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL); in sbus_iommu_init()
67 if (!iommu) { in sbus_iommu_init()
68 prom_printf("Unable to allocate iommu structure\n"); in sbus_iommu_init()
72 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
74 if (!iommu->regs) { in sbus_iommu_init()
75 prom_printf("Cannot map IOMMU registers\n"); in sbus_iommu_init()
79 control = sbus_readl(&iommu->regs->control); in sbus_iommu_init()
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| /Linux-v5.10/Documentation/userspace-api/ |
| D | iommu.rst | 2 .. iommu:
5 IOMMU Userspace API
8 IOMMU UAPI is used for virtualization cases where communications are
9 needed between physical and virtual IOMMU drivers. For baremetal
10 usage, the IOMMU is a system device which does not need to communicate
15 relies on the physical IOMMU and for this reason requires interactions
27 3. Invalidate IOMMU caches upon guest requests
32 The IOMMU UAPIs are generic and extensible to meet the following
41 Although the data structures defined in IOMMU UAPI are self-contained,
42 there are no user API functions introduced. Instead, IOMMU UAPI is
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