1Mediatek Video Codec
2
3Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
4supports high resolution encoding and decoding functionalities.
5
6Required properties:
7- compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder
8  "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
9  "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
10- reg : Physical base address of the video codec registers and length of
11  memory mapped region.
12- interrupts : interrupt number to the cpu.
13- mediatek,larb : must contain the local arbiters in the current Socs.
14- clocks : list of clock specifiers, corresponding to entries in
15  the clock-names property.
16- clock-names: encoder must contain "venc_sel_src", "venc_sel",,
17  "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll",
18  "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll",
19  "venc_lt_sel", "vdec_bus_clk_src".
20- iommus : should point to the respective IOMMU block with master port as
21  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
22  for details.
23One of the two following nodes:
24- mediatek,vpu : the node of the video processor unit, if using VPU.
25- mediatek,scp : the node of the SCP unit, if using SCP.
26
27
28Example:
29
30vcodec_dec: vcodec@16000000 {
31    compatible = "mediatek,mt8173-vcodec-dec";
32    reg = <0 0x16000000 0 0x100>,   /*VDEC_SYS*/
33          <0 0x16020000 0 0x1000>,  /*VDEC_MISC*/
34          <0 0x16021000 0 0x800>,   /*VDEC_LD*/
35          <0 0x16021800 0 0x800>,   /*VDEC_TOP*/
36          <0 0x16022000 0 0x1000>,  /*VDEC_CM*/
37          <0 0x16023000 0 0x1000>,  /*VDEC_AD*/
38          <0 0x16024000 0 0x1000>,  /*VDEC_AV*/
39          <0 0x16025000 0 0x1000>,  /*VDEC_PP*/
40          <0 0x16026800 0 0x800>,   /*VP8_VD*/
41          <0 0x16027000 0 0x800>,   /*VP6_VD*/
42          <0 0x16027800 0 0x800>,   /*VP8_VL*/
43          <0 0x16028400 0 0x400>;   /*VP9_VD*/
44    interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
45    mediatek,larb = <&larb1>;
46    iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
47             <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
48             <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
49             <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
50             <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
51             <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
52             <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
53             <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
54    mediatek,vpu = <&vpu>;
55    power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
56    clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
57             <&topckgen CLK_TOP_UNIVPLL_D2>,
58             <&topckgen CLK_TOP_CCI400_SEL>,
59             <&topckgen CLK_TOP_VDEC_SEL>,
60             <&topckgen CLK_TOP_VCODECPLL>,
61             <&apmixedsys CLK_APMIXED_VENCPLL>,
62             <&topckgen CLK_TOP_VENC_LT_SEL>,
63             <&topckgen CLK_TOP_VCODECPLL_370P5>;
64    clock-names = "vcodecpll",
65                  "univpll_d2",
66                  "clk_cci400_sel",
67                  "vdec_sel",
68                  "vdecpll",
69                  "vencpll",
70                  "venc_lt_sel",
71                  "vdec_bus_clk_src";
72    assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
73                      <&topckgen CLK_TOP_CCI400_SEL>,
74                      <&topckgen CLK_TOP_VDEC_SEL>,
75                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
76                      <&apmixedsys CLK_APMIXED_VENCPLL>;
77    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
78                             <&topckgen CLK_TOP_UNIVPLL_D2>,
79                             <&topckgen CLK_TOP_VCODECPLL>;
80    assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
81  };
82
83  vcodec_enc: vcodec@18002000 {
84    compatible = "mediatek,mt8173-vcodec-enc";
85    reg = <0 0x18002000 0 0x1000>,    /*VENC_SYS*/
86          <0 0x19002000 0 0x1000>;    /*VENC_LT_SYS*/
87    interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
88		 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
89    mediatek,larb = <&larb3>,
90		    <&larb5>;
91    iommus = <&iommu M4U_PORT_VENC_RCPU>,
92             <&iommu M4U_PORT_VENC_REC>,
93             <&iommu M4U_PORT_VENC_BSDMA>,
94             <&iommu M4U_PORT_VENC_SV_COMV>,
95             <&iommu M4U_PORT_VENC_RD_COMV>,
96             <&iommu M4U_PORT_VENC_CUR_LUMA>,
97             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
98             <&iommu M4U_PORT_VENC_REF_LUMA>,
99             <&iommu M4U_PORT_VENC_REF_CHROMA>,
100             <&iommu M4U_PORT_VENC_NBM_RDMA>,
101             <&iommu M4U_PORT_VENC_NBM_WDMA>,
102             <&iommu M4U_PORT_VENC_RCPU_SET2>,
103             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
104             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
105             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
106             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
107             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
108             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
109             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
110             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
111    mediatek,vpu = <&vpu>;
112    clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
113             <&topckgen CLK_TOP_VENC_SEL>,
114             <&topckgen CLK_TOP_UNIVPLL1_D2>,
115             <&topckgen CLK_TOP_VENC_LT_SEL>;
116    clock-names = "venc_sel_src",
117                  "venc_sel",
118                  "venc_lt_sel_src",
119                  "venc_lt_sel";
120    assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
121                      <&topckgen CLK_TOP_VENC_LT_SEL>;
122    assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
123                             <&topckgen CLK_TOP_UNIVPLL1_D2>;
124  };
125