18 #include <linux/iommu.h>
55 static int __enable_clocks(struct msm_iommu_dev *iommu)  in __enable_clocks()  argument
59 	ret = clk_enable(iommu->pclk);  in __enable_clocks()
63 	if (iommu->clk) {  in __enable_clocks()
64 		ret = clk_enable(iommu->clk);  in __enable_clocks()
66 			clk_disable(iommu->pclk);  in __enable_clocks()
72 static void __disable_clocks(struct msm_iommu_dev *iommu)  in __disable_clocks()  argument
74 	if (iommu->clk)  in __disable_clocks()
75 		clk_disable(iommu->clk);  in __disable_clocks()
76 	clk_disable(iommu->pclk);  in __disable_clocks()
121 	struct msm_iommu_dev *iommu = NULL;  in __flush_iotlb()  local
125 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in __flush_iotlb()
126 		ret = __enable_clocks(iommu);  in __flush_iotlb()
130 		list_for_each_entry(master, &iommu->ctx_list, list)  in __flush_iotlb()
131 			SET_CTX_TLBIALL(iommu->base, master->num, 0);  in __flush_iotlb()
133 		__disable_clocks(iommu);  in __flush_iotlb()
143 	struct msm_iommu_dev *iommu = NULL;  in __flush_iotlb_range()  local
148 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in __flush_iotlb_range()
149 		ret = __enable_clocks(iommu);  in __flush_iotlb_range()
153 		list_for_each_entry(master, &iommu->ctx_list, list) {  in __flush_iotlb_range()
157 				iova |= GET_CONTEXTIDR_ASID(iommu->base,  in __flush_iotlb_range()
159 				SET_TLBIVA(iommu->base, master->num, iova);  in __flush_iotlb_range()
164 		__disable_clocks(iommu);  in __flush_iotlb_range()
214 static void config_mids(struct msm_iommu_dev *iommu,  in config_mids()  argument
223 		SET_M2VCBR_N(iommu->base, mid, 0);  in config_mids()
224 		SET_CBACR_N(iommu->base, ctx, 0);  in config_mids()
227 		SET_VMID(iommu->base, mid, 0);  in config_mids()
230 		SET_CBNDX(iommu->base, mid, ctx);  in config_mids()
233 		SET_CBVMID(iommu->base, ctx, 0);  in config_mids()
236 		SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);  in config_mids()
239 		SET_NSCFG(iommu->base, mid, 3);  in config_mids()
375 	struct msm_iommu_dev *iommu, *ret = NULL;  in find_iommu_for_dev()  local
378 	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {  in find_iommu_for_dev()
379 		master = list_first_entry(&iommu->ctx_list,  in find_iommu_for_dev()
383 			ret = iommu;  in find_iommu_for_dev()
393 	struct msm_iommu_dev *iommu;  in msm_iommu_probe_device()  local
397 	iommu = find_iommu_for_dev(dev);  in msm_iommu_probe_device()
400 	if (!iommu)  in msm_iommu_probe_device()
403 	return &iommu->iommu;  in msm_iommu_probe_device()
414 	struct msm_iommu_dev *iommu;  in msm_iommu_attach_dev()  local
422 	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {  in msm_iommu_attach_dev()
423 		master = list_first_entry(&iommu->ctx_list,  in msm_iommu_attach_dev()
427 			ret = __enable_clocks(iommu);  in msm_iommu_attach_dev()
431 			list_for_each_entry(master, &iommu->ctx_list, list) {  in msm_iommu_attach_dev()
438 					msm_iommu_alloc_ctx(iommu->context_map,  in msm_iommu_attach_dev()
439 							    0, iommu->ncb);  in msm_iommu_attach_dev()
444 				config_mids(iommu, master);  in msm_iommu_attach_dev()
445 				__program_context(iommu->base, master->num,  in msm_iommu_attach_dev()
448 			__disable_clocks(iommu);  in msm_iommu_attach_dev()
449 			list_add(&iommu->dom_node, &priv->list_attached);  in msm_iommu_attach_dev()
464 	struct msm_iommu_dev *iommu;  in msm_iommu_detach_dev()  local
471 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in msm_iommu_detach_dev()
472 		ret = __enable_clocks(iommu);  in msm_iommu_detach_dev()
476 		list_for_each_entry(master, &iommu->ctx_list, list) {  in msm_iommu_detach_dev()
477 			msm_iommu_free_ctx(iommu->context_map, master->num);  in msm_iommu_detach_dev()
478 			__reset_context(iommu->base, master->num);  in msm_iommu_detach_dev()
480 		__disable_clocks(iommu);  in msm_iommu_detach_dev()
517 	struct msm_iommu_dev *iommu;  in msm_iommu_iova_to_phys()  local
526 	iommu = list_first_entry(&priv->list_attached,  in msm_iommu_iova_to_phys()
529 	if (list_empty(&iommu->ctx_list))  in msm_iommu_iova_to_phys()
532 	master = list_first_entry(&iommu->ctx_list,  in msm_iommu_iova_to_phys()
537 	ret = __enable_clocks(iommu);  in msm_iommu_iova_to_phys()
542 	SET_CTX_TLBIALL(iommu->base, master->num, 0);  in msm_iommu_iova_to_phys()
543 	SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);  in msm_iommu_iova_to_phys()
545 	par = GET_PAR(iommu->base, master->num);  in msm_iommu_iova_to_phys()
548 	if (GET_NOFAULT_SS(iommu->base, master->num))  in msm_iommu_iova_to_phys()
553 	if (GET_FAULT(iommu->base, master->num))  in msm_iommu_iova_to_phys()
556 	__disable_clocks(iommu);  in msm_iommu_iova_to_phys()
593 				struct msm_iommu_dev **iommu,  in insert_iommu_master()  argument
599 	if (list_empty(&(*iommu)->ctx_list)) {  in insert_iommu_master()
602 		list_add(&master->list, &(*iommu)->ctx_list);  in insert_iommu_master()
619 	struct msm_iommu_dev *iommu;  in qcom_iommu_of_xlate()  local
624 	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node)  in qcom_iommu_of_xlate()
625 		if (iommu->dev->of_node == spec->np)  in qcom_iommu_of_xlate()
628 	if (!iommu || iommu->dev->of_node != spec->np) {  in qcom_iommu_of_xlate()
633 	insert_iommu_master(dev, &iommu, spec);  in qcom_iommu_of_xlate()
642 	struct msm_iommu_dev *iommu = dev_id;  in msm_iommu_fault_handler()  local
648 	if (!iommu) {  in msm_iommu_fault_handler()
653 	pr_err("Unexpected IOMMU page fault!\n");  in msm_iommu_fault_handler()
654 	pr_err("base = %08x\n", (unsigned int)iommu->base);  in msm_iommu_fault_handler()
656 	ret = __enable_clocks(iommu);  in msm_iommu_fault_handler()
660 	for (i = 0; i < iommu->ncb; i++) {  in msm_iommu_fault_handler()
661 		fsr = GET_FSR(iommu->base, i);  in msm_iommu_fault_handler()
665 			print_ctx_regs(iommu->base, i);  in msm_iommu_fault_handler()
666 			SET_FSR(iommu->base, i, 0x4000000F);  in msm_iommu_fault_handler()
669 	__disable_clocks(iommu);  in msm_iommu_fault_handler()
686 	 * taken care when the iommu client does a writel before
702 	struct msm_iommu_dev *iommu;  in msm_iommu_probe()  local
705 	iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);  in msm_iommu_probe()
706 	if (!iommu)  in msm_iommu_probe()
709 	iommu->dev = &pdev->dev;  in msm_iommu_probe()
710 	INIT_LIST_HEAD(&iommu->ctx_list);  in msm_iommu_probe()
712 	iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");  in msm_iommu_probe()
713 	if (IS_ERR(iommu->pclk)) {  in msm_iommu_probe()
714 		dev_err(iommu->dev, "could not get smmu_pclk\n");  in msm_iommu_probe()
715 		return PTR_ERR(iommu->pclk);  in msm_iommu_probe()
718 	ret = clk_prepare(iommu->pclk);  in msm_iommu_probe()
720 		dev_err(iommu->dev, "could not prepare smmu_pclk\n");  in msm_iommu_probe()
724 	iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");  in msm_iommu_probe()
725 	if (IS_ERR(iommu->clk)) {  in msm_iommu_probe()
726 		dev_err(iommu->dev, "could not get iommu_clk\n");  in msm_iommu_probe()
727 		clk_unprepare(iommu->pclk);  in msm_iommu_probe()
728 		return PTR_ERR(iommu->clk);  in msm_iommu_probe()
731 	ret = clk_prepare(iommu->clk);  in msm_iommu_probe()
733 		dev_err(iommu->dev, "could not prepare iommu_clk\n");  in msm_iommu_probe()
734 		clk_unprepare(iommu->pclk);  in msm_iommu_probe()
739 	iommu->base = devm_ioremap_resource(iommu->dev, r);  in msm_iommu_probe()
740 	if (IS_ERR(iommu->base)) {  in msm_iommu_probe()
741 		dev_err(iommu->dev, "could not get iommu base\n");  in msm_iommu_probe()
742 		ret = PTR_ERR(iommu->base);  in msm_iommu_probe()
747 	iommu->irq = platform_get_irq(pdev, 0);  in msm_iommu_probe()
748 	if (iommu->irq < 0) {  in msm_iommu_probe()
753 	ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);  in msm_iommu_probe()
755 		dev_err(iommu->dev, "could not get ncb\n");  in msm_iommu_probe()
758 	iommu->ncb = val;  in msm_iommu_probe()
760 	msm_iommu_reset(iommu->base, iommu->ncb);  in msm_iommu_probe()
761 	SET_M(iommu->base, 0, 1);  in msm_iommu_probe()
762 	SET_PAR(iommu->base, 0, 0);  in msm_iommu_probe()
763 	SET_V2PCFG(iommu->base, 0, 1);  in msm_iommu_probe()
764 	SET_V2PPR(iommu->base, 0, 0);  in msm_iommu_probe()
765 	par = GET_PAR(iommu->base, 0);  in msm_iommu_probe()
766 	SET_V2PCFG(iommu->base, 0, 0);  in msm_iommu_probe()
767 	SET_M(iommu->base, 0, 0);  in msm_iommu_probe()
775 	ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,  in msm_iommu_probe()
779 					iommu);  in msm_iommu_probe()
781 		pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);  in msm_iommu_probe()
785 	list_add(&iommu->dev_node, &qcom_iommu_devices);  in msm_iommu_probe()
787 	ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,  in msm_iommu_probe()
794 	iommu_device_set_ops(&iommu->iommu, &msm_iommu_ops);  in msm_iommu_probe()
795 	iommu_device_set_fwnode(&iommu->iommu, &pdev->dev.of_node->fwnode);  in msm_iommu_probe()
797 	ret = iommu_device_register(&iommu->iommu);  in msm_iommu_probe()
806 		iommu->base, iommu->irq, iommu->ncb);  in msm_iommu_probe()
810 	clk_unprepare(iommu->clk);  in msm_iommu_probe()
811 	clk_unprepare(iommu->pclk);  in msm_iommu_probe()
816 	{ .compatible = "qcom,apq8064-iommu" },
822 	struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);  in msm_iommu_remove()  local
824 	clk_unprepare(iommu->clk);  in msm_iommu_remove()
825 	clk_unprepare(iommu->pclk);  in msm_iommu_remove()
844 		pr_err("Failed to register IOMMU driver\n");  in msm_iommu_driver_init()