Lines Matching full:iommu

1 * QCOM IOMMU
3 The MSM IOMMU is an implementation compatible with the ARM VMSA short
5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9   - compatible: Must contain "qcom,apq8064-iommu".
10   - reg: Base address and size of the IOMMU registers.
15   - #iommu-cells: The number of cells needed to specify the stream id. This
17   - qcom,ncb:	  The total number of context banks in the IOMMU.
27 		  required for iommu's register accesses.
29 		  required by iommu for bus accesses.
31 Each bus master connected to an IOMMU must reference the IOMMU in its device
34   - iommus: A reference to the IOMMU in multiple cells. The first cell is a
35 	    phandle to the IOMMU and the second cell is the stream id.
36 	    A single master device can be connected to more than one iommu
37 	    and multiple contexts in each of the iommu. So multiple entries
41 Example: mdp iommu and its bus master
43                 mdp_port0: iommu@7500000 {
44 			compatible = "qcom,apq8064-iommu";
45 			#iommu-cells = <1>;