| /Linux-v6.1/drivers/gpu/drm/i915/ |
| D | intel_pch.c | 12 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) in intel_pch_type() argument
16 drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n"); in intel_pch_type()
17 drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5); in intel_pch_type()
20 drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n"); in intel_pch_type()
21 drm_WARN_ON(&dev_priv->drm, in intel_pch_type()
22 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
25 drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n"); in intel_pch_type()
26 drm_WARN_ON(&dev_priv->drm, in intel_pch_type()
27 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
31 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n"); in intel_pch_type()
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| D | i915_drv.h | 462 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) argument
463 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) argument
464 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) argument
466 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) argument
486 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision) argument
488 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) argument
573 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) argument
574 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) argument
576 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) argument
577 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) argument
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| D | i915_irq.c | 186 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) in intel_hpd_init_pins() argument
188 struct intel_hotplug *hpd = &dev_priv->display.hotplug; in intel_hpd_init_pins()
190 if (HAS_GMCH(dev_priv)) { in intel_hpd_init_pins()
191 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
192 IS_CHERRYVIEW(dev_priv)) in intel_hpd_init_pins()
199 if (DISPLAY_VER(dev_priv) >= 11) in intel_hpd_init_pins()
201 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_hpd_init_pins()
203 else if (DISPLAY_VER(dev_priv) >= 8) in intel_hpd_init_pins()
205 else if (DISPLAY_VER(dev_priv) >= 7) in intel_hpd_init_pins()
210 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && in intel_hpd_init_pins()
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| D | i915_driver.c | 115 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) in i915_get_bridge_dev() argument
117 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); in i915_get_bridge_dev()
119 dev_priv->bridge_dev = in i915_get_bridge_dev()
121 if (!dev_priv->bridge_dev) { in i915_get_bridge_dev()
122 drm_err(&dev_priv->drm, "bridge device not found\n"); in i915_get_bridge_dev()
126 return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev, in i915_get_bridge_dev()
127 dev_priv->bridge_dev); in i915_get_bridge_dev()
132 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) in intel_alloc_mchbar_resource() argument
134 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource()
139 if (GRAPHICS_VER(dev_priv) >= 4) in intel_alloc_mchbar_resource()
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| D | i915_suspend.c | 36 static void intel_save_swf(struct drm_i915_private *dev_priv) in intel_save_swf() argument
41 if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { in intel_save_swf()
43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
48 } else if (GRAPHICS_VER(dev_priv) == 2) { in intel_save_swf()
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
51 } else if (HAS_GMCH(dev_priv)) { in intel_save_swf()
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
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| D | intel_pch.h | 67 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) argument
68 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) argument
69 #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP) argument
70 #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) argument
71 #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) argument
72 #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) argument
73 #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) argument
74 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) argument
75 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) argument
76 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) argument
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| D | intel_pm.c | 51 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) in gen9_init_clock_gating() argument
53 if (HAS_LLC(dev_priv)) { in gen9_init_clock_gating()
61 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1, in gen9_init_clock_gating()
62 intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | in gen9_init_clock_gating()
67 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1, in gen9_init_clock_gating()
68 intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
71 intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, in gen9_init_clock_gating()
72 intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); in gen9_init_clock_gating()
78 …intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_… in gen9_init_clock_gating()
82 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) in bxt_init_clock_gating() argument
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| /Linux-v6.1/drivers/gpu/drm/savage/ |
| D | savage_bci.c | 47 savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_shadow() argument
49 uint32_t mask = dev_priv->status_used_mask; in savage_bci_wait_fifo_shadow()
50 uint32_t threshold = dev_priv->bci_threshold_hi; in savage_bci_wait_fifo_shadow()
55 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) in savage_bci_wait_fifo_shadow()
62 status = dev_priv->status_ptr[0]; in savage_bci_wait_fifo_shadow()
76 savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_s3d() argument
78 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s3d()
97 savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_s4() argument
99 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s4()
129 savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e) in savage_bci_wait_event_shadow() argument
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| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_display_power_well.c | 145 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, in intel_display_power_well_is_enabled() argument
150 power_well = lookup_power_well(dev_priv, power_well_id); in intel_display_power_well_is_enabled()
152 return intel_power_well_is_enabled(dev_priv, power_well); in intel_display_power_well_is_enabled()
181 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, in hsw_power_well_post_enable() argument
185 intel_vga_reset_io_mem(dev_priv); in hsw_power_well_post_enable()
188 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); in hsw_power_well_post_enable()
191 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, in hsw_power_well_pre_disable() argument
195 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); in hsw_power_well_pre_disable()
213 aux_ch_to_digital_port(struct drm_i915_private *dev_priv, in aux_ch_to_digital_port() argument
219 for_each_intel_encoder(&dev_priv->drm, encoder) { in aux_ch_to_digital_port()
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| D | intel_fifo_underrun.c | 57 struct drm_i915_private *dev_priv = to_i915(dev); in ivb_can_enable_err_int() local
61 lockdep_assert_held(&dev_priv->irq_lock); in ivb_can_enable_err_int()
63 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
64 crtc = intel_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
75 struct drm_i915_private *dev_priv = to_i915(dev); in cpt_can_enable_serr_int() local
79 lockdep_assert_held(&dev_priv->irq_lock); in cpt_can_enable_serr_int()
81 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
82 crtc = intel_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
93 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_check_fifo_underruns() local
97 lockdep_assert_held(&dev_priv->irq_lock); in i9xx_check_fifo_underruns()
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| D | intel_pch_refclk.c | 12 static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv) in lpt_fdi_reset_mphy() argument
16 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); in lpt_fdi_reset_mphy()
18 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); in lpt_fdi_reset_mphy()
20 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
22 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); in lpt_fdi_reset_mphy()
24 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); in lpt_fdi_reset_mphy()
26 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); in lpt_fdi_reset_mphy()
28 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
30 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); in lpt_fdi_reset_mphy()
34 static void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv) in lpt_fdi_program_mphy() argument
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| D | intel_cdclk.c | 79 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, in intel_cdclk_get_cdclk() argument
82 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
85 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, in intel_cdclk_set_cdclk() argument
89 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
92 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv, in intel_cdclk_modeset_calc_cdclk() argument
95 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
98 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, in intel_cdclk_calc_voltage_level() argument
101 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
104 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_133mhz_get_cdclk() argument
110 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_200mhz_get_cdclk() argument
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| D | intel_fdi.c | 20 static void assert_fdi_tx(struct drm_i915_private *dev_priv, in assert_fdi_tx() argument
25 if (HAS_DDI(dev_priv)) { in assert_fdi_tx()
33 cur_state = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; in assert_fdi_tx()
35 cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; in assert_fdi_tx()
52 static void assert_fdi_rx(struct drm_i915_private *dev_priv, in assert_fdi_rx() argument
57 cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; in assert_fdi_rx()
114 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fdi_link_train() local
116 dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state); in intel_fdi_link_train()
131 struct drm_i915_private *dev_priv = to_i915(dev); in ilk_check_fdi_lanes() local
136 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
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| D | intel_pch_display.c | 34 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, in assert_pch_dp_disabled() argument
41 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); in assert_pch_dp_disabled()
47 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
52 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, in assert_pch_hdmi_disabled() argument
59 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); in assert_pch_hdmi_disabled()
65 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
70 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, in assert_pch_ports_disabled() argument
75 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); in assert_pch_ports_disabled()
76 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); in assert_pch_ports_disabled()
77 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); in assert_pch_ports_disabled()
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| D | intel_display_power.c | 200 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, in __intel_display_power_is_enabled() argument
206 if (dev_priv->runtime_pm.suspended) in __intel_display_power_is_enabled()
211 for_each_power_domain_well_reverse(dev_priv, power_well, domain) { in __intel_display_power_is_enabled()
241 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, in intel_display_power_is_enabled() argument
247 power_domains = &dev_priv->display.power.domains; in intel_display_power_is_enabled()
250 ret = __intel_display_power_is_enabled(dev_priv, domain); in intel_display_power_is_enabled()
257 sanitize_target_dc_state(struct drm_i915_private *dev_priv, in sanitize_target_dc_state() argument
272 if (dev_priv->display.dmc.allowed_dc_mask & target_dc_state) in sanitize_target_dc_state()
290 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, in intel_display_power_set_target_dc_state() argument
295 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; in intel_display_power_set_target_dc_state()
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| D | intel_hotplug.c | 87 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, in intel_hpd_pin_default() argument
140 static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv, in intel_hpd_irq_storm_detect() argument
143 struct intel_hotplug *hpd = &dev_priv->display.hotplug; in intel_hpd_irq_storm_detect()
151 (!long_hpd && !dev_priv->display.hotplug.hpd_short_storm_enabled)) in intel_hpd_irq_storm_detect()
162 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
166 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
176 intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv) in intel_hpd_irq_storm_switch_to_polling() argument
178 struct drm_device *dev = &dev_priv->drm; in intel_hpd_irq_storm_switch_to_polling()
183 lockdep_assert_held(&dev_priv->irq_lock); in intel_hpd_irq_storm_switch_to_polling()
194 dev_priv->display.hotplug.stats[pin].state != HPD_MARK_DISABLED) in intel_hpd_irq_storm_switch_to_polling()
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| D | intel_combo_phy.c | 54 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in icl_get_procmon_ref_values() argument
59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
84 static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv, in icl_set_procmon_ref_values() argument
90 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_set_procmon_ref_values()
92 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in icl_set_procmon_ref_values()
95 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); in icl_set_procmon_ref_values()
97 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
98 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
101 static bool check_phy_reg(struct drm_i915_private *dev_priv, in check_phy_reg() argument
105 u32 val = intel_de_read(dev_priv, reg); in check_phy_reg()
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| D | intel_dpio_phy.c | 219 bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count) in bxt_get_phy_list() argument
221 if (IS_GEMINILAKE(dev_priv)) { in bxt_get_phy_list()
231 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy) in bxt_get_phy_info() argument
235 bxt_get_phy_list(dev_priv, &count); in bxt_get_phy_info()
240 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, in bxt_port_to_phy_channel() argument
246 phys = bxt_get_phy_list(dev_priv, &count); in bxt_port_to_phy_channel()
265 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c", in bxt_port_to_phy_channel()
274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_ddi_phy_set_signal_levels() local
283 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in bxt_ddi_phy_set_signal_levels()
286 bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch); in bxt_ddi_phy_set_signal_levels()
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| D | vlv_dsi.c | 88 struct drm_i915_private *dev_priv = to_i915(dev); in vlv_dsi_wait_for_fifo_empty() local
94 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), in vlv_dsi_wait_for_fifo_empty()
96 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
99 static void write_data(struct drm_i915_private *dev_priv, in write_data() argument
111 intel_de_write(dev_priv, reg, val); in write_data()
115 static void read_data(struct drm_i915_private *dev_priv, in read_data() argument
122 u32 val = intel_de_read(dev_priv, reg); in read_data()
134 struct drm_i915_private *dev_priv = to_i915(dev); in intel_dsi_host_transfer() local
163 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), in intel_dsi_host_transfer()
165 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
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| /Linux-v6.1/drivers/gpu/drm/vmwgfx/ |
| D | vmwgfx_drv.c | 361 static void vmw_print_sm_type(struct vmw_private *dev_priv) in vmw_print_sm_type() argument
372 drm_info(&dev_priv->drm, "Available shader model: %s.\n", in vmw_print_sm_type()
373 names[dev_priv->sm_type]); in vmw_print_sm_type()
389 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) in vmw_dummy_query_bo_create() argument
402 ret = vmw_bo_create(dev_priv, PAGE_SIZE, in vmw_dummy_query_bo_create()
427 dev_priv->dummy_query_bo = vbo; in vmw_dummy_query_bo_create()
432 static int vmw_device_init(struct vmw_private *dev_priv) in vmw_device_init() argument
436 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_device_init()
437 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); in vmw_device_init()
438 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_device_init()
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| D | vmwgfx_irq.c | 57 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_thread_fn() local
61 dev_priv->irqthread_pending)) { in vmw_thread_fn()
62 vmw_fences_update(dev_priv->fman); in vmw_thread_fn()
63 wake_up_all(&dev_priv->fence_queue); in vmw_thread_fn()
68 dev_priv->irqthread_pending)) { in vmw_thread_fn()
69 vmw_cmdbuf_irqthread(dev_priv->cman); in vmw_thread_fn()
90 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_irq_handler() local
94 status = vmw_irq_status_read(dev_priv); in vmw_irq_handler()
95 masked_status = status & READ_ONCE(dev_priv->irq_mask); in vmw_irq_handler()
98 vmw_irq_status_write(dev_priv, status); in vmw_irq_handler()
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| D | vmwgfx_cmd.c | 35 bool vmw_supports_3d(struct vmw_private *dev_priv) in vmw_supports_3d() argument
38 const struct vmw_fifo_state *fifo = dev_priv->fifo; in vmw_supports_3d()
40 if (!(dev_priv->capabilities & SVGA_CAP_3D)) in vmw_supports_3d()
43 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { in vmw_supports_3d()
46 if (!dev_priv->has_mob) in vmw_supports_3d()
49 result = vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_3D); in vmw_supports_3d()
54 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) in vmw_supports_3d()
57 BUG_ON(vmw_is_svga_v3(dev_priv)); in vmw_supports_3d()
59 fifo_min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN); in vmw_supports_3d()
63 hwversion = vmw_fifo_mem_read(dev_priv, in vmw_supports_3d()
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| /Linux-v6.1/drivers/gpu/drm/r128/ |
| D | r128_cce.c | 56 drm_r128_private_t *dev_priv = dev->dev_private; in R128_READ_PLL() local
63 static void r128_status(drm_r128_private_t *dev_priv) in r128_status() argument
84 static int r128_do_pixcache_flush(drm_r128_private_t *dev_priv) in r128_do_pixcache_flush() argument
92 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_pixcache_flush()
104 static int r128_do_wait_for_fifo(drm_r128_private_t *dev_priv, int entries) in r128_do_wait_for_fifo() argument
108 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_fifo()
121 static int r128_do_wait_for_idle(drm_r128_private_t *dev_priv) in r128_do_wait_for_idle() argument
125 ret = r128_do_wait_for_fifo(dev_priv, 64); in r128_do_wait_for_idle()
129 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_idle()
131 r128_do_pixcache_flush(dev_priv); in r128_do_wait_for_idle()
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| /Linux-v6.1/drivers/gpu/drm/mga/ |
| D | mga_dma.c | 53 int mga_do_wait_for_idle(drm_mga_private_t *dev_priv) in mga_do_wait_for_idle() argument
59 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_wait_for_idle()
75 static int mga_do_dma_reset(drm_mga_private_t *dev_priv) in mga_do_dma_reset() argument
77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_do_dma_reset()
78 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_reset()
103 void mga_do_dma_flush(drm_mga_private_t *dev_priv) in mga_do_dma_flush() argument
105 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_flush()
113 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_dma_flush()
125 tail = primary->tail + dev_priv->primary->offset; in mga_do_dma_flush()
148 DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset)); in mga_do_dma_flush()
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| /Linux-v6.1/drivers/gpu/drm/gma500/ |
| D | psb_drv.c | 103 static void psb_spank(struct drm_psb_private *dev_priv) in psb_spank() argument
124 PSB_WSGX32(dev_priv->gtt.gatt_start, PSB_CR_BIF_TWOD_REQ_BASE); in psb_spank()
129 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_do_init() local
130 struct psb_gtt *pg = &dev_priv->gtt; in psb_do_init()
143 dev_priv->gatt_free_offset = pg->mmu_gatt_start + in psb_do_init()
146 spin_lock_init(&dev_priv->irqmask_lock); in psb_do_init()
157 psb_spank(dev_priv); in psb_do_init()
168 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_driver_unload() local
177 if (dev_priv->ops->chip_teardown) in psb_driver_unload()
178 dev_priv->ops->chip_teardown(dev); in psb_driver_unload()
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