20 static void assert_fdi_tx(struct drm_i915_private *dev_priv,  in assert_fdi_tx()  argument
25 	if (HAS_DDI(dev_priv)) {  in assert_fdi_tx()
33 		cur_state = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;  in assert_fdi_tx()
35 		cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;  in assert_fdi_tx()
52 static void assert_fdi_rx(struct drm_i915_private *dev_priv,  in assert_fdi_rx()  argument
57 	cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;  in assert_fdi_rx()
114 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_fdi_link_train()  local
116 	dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state);  in intel_fdi_link_train()
131 	struct drm_i915_private *dev_priv = to_i915(dev);  in ilk_check_fdi_lanes()  local
136 	drm_dbg_kms(&dev_priv->drm,  in ilk_check_fdi_lanes()
140 		drm_dbg_kms(&dev_priv->drm,  in ilk_check_fdi_lanes()
146 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {  in ilk_check_fdi_lanes()
148 			drm_dbg_kms(&dev_priv->drm,  in ilk_check_fdi_lanes()
157 	if (INTEL_NUM_PIPES(dev_priv) == 2)  in ilk_check_fdi_lanes()
168 		other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_C);  in ilk_check_fdi_lanes()
175 			drm_dbg_kms(&dev_priv->drm,  in ilk_check_fdi_lanes()
183 			drm_dbg_kms(&dev_priv->drm,  in ilk_check_fdi_lanes()
189 		other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_B);  in ilk_check_fdi_lanes()
196 			drm_dbg_kms(&dev_priv->drm,  in ilk_check_fdi_lanes()
282 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)  in cpt_set_fdi_bc_bifurcation()  argument
286 	temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);  in cpt_set_fdi_bc_bifurcation()
290 	drm_WARN_ON(&dev_priv->drm,  in cpt_set_fdi_bc_bifurcation()
291 		    intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &  in cpt_set_fdi_bc_bifurcation()
293 	drm_WARN_ON(&dev_priv->drm,  in cpt_set_fdi_bc_bifurcation()
294 		    intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &  in cpt_set_fdi_bc_bifurcation()
301 	drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",  in cpt_set_fdi_bc_bifurcation()
303 	intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);  in cpt_set_fdi_bc_bifurcation()
304 	intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);  in cpt_set_fdi_bc_bifurcation()
310 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ivb_update_fdi_bc_bifurcation()  local
317 			cpt_set_fdi_bc_bifurcation(dev_priv, false);  in ivb_update_fdi_bc_bifurcation()
319 			cpt_set_fdi_bc_bifurcation(dev_priv, true);  in ivb_update_fdi_bc_bifurcation()
323 		cpt_set_fdi_bc_bifurcation(dev_priv, true);  in ivb_update_fdi_bc_bifurcation()
334 	struct drm_i915_private *dev_priv = to_i915(dev);  in intel_fdi_normal_train()  local
341 	temp = intel_de_read(dev_priv, reg);  in intel_fdi_normal_train()
342 	if (IS_IVYBRIDGE(dev_priv)) {  in intel_fdi_normal_train()
349 	intel_de_write(dev_priv, reg, temp);  in intel_fdi_normal_train()
352 	temp = intel_de_read(dev_priv, reg);  in intel_fdi_normal_train()
353 	if (HAS_PCH_CPT(dev_priv)) {  in intel_fdi_normal_train()
360 	intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);  in intel_fdi_normal_train()
363 	intel_de_posting_read(dev_priv, reg);  in intel_fdi_normal_train()
367 	if (IS_IVYBRIDGE(dev_priv))  in intel_fdi_normal_train()
368 		intel_de_write(dev_priv, reg,  in intel_fdi_normal_train()
369 			       intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);  in intel_fdi_normal_train()
377 	struct drm_i915_private *dev_priv = to_i915(dev);  in ilk_fdi_link_train()  local
386 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),  in ilk_fdi_link_train()
387 		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);  in ilk_fdi_link_train()
390 	assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder);  in ilk_fdi_link_train()
395 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_link_train()
398 	intel_de_write(dev_priv, reg, temp);  in ilk_fdi_link_train()
399 	intel_de_read(dev_priv, reg);  in ilk_fdi_link_train()
404 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_link_train()
409 	intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);  in ilk_fdi_link_train()
412 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_link_train()
415 	intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);  in ilk_fdi_link_train()
417 	intel_de_posting_read(dev_priv, reg);  in ilk_fdi_link_train()
421 	intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),  in ilk_fdi_link_train()
423 	intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),  in ilk_fdi_link_train()
428 		temp = intel_de_read(dev_priv, reg);  in ilk_fdi_link_train()
429 		drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);  in ilk_fdi_link_train()
432 			drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");  in ilk_fdi_link_train()
433 			intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);  in ilk_fdi_link_train()
438 		drm_err(&dev_priv->drm, "FDI train 1 fail!\n");  in ilk_fdi_link_train()
442 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_link_train()
445 	intel_de_write(dev_priv, reg, temp);  in ilk_fdi_link_train()
448 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_link_train()
451 	intel_de_write(dev_priv, reg, temp);  in ilk_fdi_link_train()
453 	intel_de_posting_read(dev_priv, reg);  in ilk_fdi_link_train()
458 		temp = intel_de_read(dev_priv, reg);  in ilk_fdi_link_train()
459 		drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);  in ilk_fdi_link_train()
462 			intel_de_write(dev_priv, reg,  in ilk_fdi_link_train()
464 			drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");  in ilk_fdi_link_train()
469 		drm_err(&dev_priv->drm, "FDI train 2 fail!\n");  in ilk_fdi_link_train()
471 	drm_dbg_kms(&dev_priv->drm, "FDI train done\n");  in ilk_fdi_link_train()
487 	struct drm_i915_private *dev_priv = to_i915(dev);  in gen6_fdi_link_train()  local
496 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),  in gen6_fdi_link_train()
497 		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);  in gen6_fdi_link_train()
502 	temp = intel_de_read(dev_priv, reg);  in gen6_fdi_link_train()
505 	intel_de_write(dev_priv, reg, temp);  in gen6_fdi_link_train()
507 	intel_de_posting_read(dev_priv, reg);  in gen6_fdi_link_train()
512 	temp = intel_de_read(dev_priv, reg);  in gen6_fdi_link_train()
520 	intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);  in gen6_fdi_link_train()
522 	intel_de_write(dev_priv, FDI_RX_MISC(pipe),  in gen6_fdi_link_train()
526 	temp = intel_de_read(dev_priv, reg);  in gen6_fdi_link_train()
527 	if (HAS_PCH_CPT(dev_priv)) {  in gen6_fdi_link_train()
534 	intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);  in gen6_fdi_link_train()
536 	intel_de_posting_read(dev_priv, reg);  in gen6_fdi_link_train()
541 		temp = intel_de_read(dev_priv, reg);  in gen6_fdi_link_train()
544 		intel_de_write(dev_priv, reg, temp);  in gen6_fdi_link_train()
546 		intel_de_posting_read(dev_priv, reg);  in gen6_fdi_link_train()
551 			temp = intel_de_read(dev_priv, reg);  in gen6_fdi_link_train()
552 			drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);  in gen6_fdi_link_train()
554 				intel_de_write(dev_priv, reg,  in gen6_fdi_link_train()
556 				drm_dbg_kms(&dev_priv->drm,  in gen6_fdi_link_train()
566 		drm_err(&dev_priv->drm, "FDI train 1 fail!\n");  in gen6_fdi_link_train()
570 	temp = intel_de_read(dev_priv, reg);  in gen6_fdi_link_train()
573 	if (IS_SANDYBRIDGE(dev_priv)) {  in gen6_fdi_link_train()
578 	intel_de_write(dev_priv, reg, temp);  in gen6_fdi_link_train()
581 	temp = intel_de_read(dev_priv, reg);  in gen6_fdi_link_train()
582 	if (HAS_PCH_CPT(dev_priv)) {  in gen6_fdi_link_train()
589 	intel_de_write(dev_priv, reg, temp);  in gen6_fdi_link_train()
591 	intel_de_posting_read(dev_priv, reg);  in gen6_fdi_link_train()
596 		temp = intel_de_read(dev_priv, reg);  in gen6_fdi_link_train()
599 		intel_de_write(dev_priv, reg, temp);  in gen6_fdi_link_train()
601 		intel_de_posting_read(dev_priv, reg);  in gen6_fdi_link_train()
606 			temp = intel_de_read(dev_priv, reg);  in gen6_fdi_link_train()
607 			drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);  in gen6_fdi_link_train()
609 				intel_de_write(dev_priv, reg,  in gen6_fdi_link_train()
611 				drm_dbg_kms(&dev_priv->drm,  in gen6_fdi_link_train()
621 		drm_err(&dev_priv->drm, "FDI train 2 fail!\n");  in gen6_fdi_link_train()
623 	drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");  in gen6_fdi_link_train()
631 	struct drm_i915_private *dev_priv = to_i915(dev);  in ivb_manual_fdi_link_train()  local
642 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),  in ivb_manual_fdi_link_train()
643 		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);  in ivb_manual_fdi_link_train()
648 	temp = intel_de_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
651 	intel_de_write(dev_priv, reg, temp);  in ivb_manual_fdi_link_train()
653 	intel_de_posting_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
656 	drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",  in ivb_manual_fdi_link_train()
657 		    intel_de_read(dev_priv, FDI_RX_IIR(pipe)));  in ivb_manual_fdi_link_train()
663 		temp = intel_de_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
666 		intel_de_write(dev_priv, reg, temp);  in ivb_manual_fdi_link_train()
669 		temp = intel_de_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
673 		intel_de_write(dev_priv, reg, temp);  in ivb_manual_fdi_link_train()
677 		temp = intel_de_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
684 		intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);  in ivb_manual_fdi_link_train()
686 		intel_de_write(dev_priv, FDI_RX_MISC(pipe),  in ivb_manual_fdi_link_train()
690 		temp = intel_de_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
693 		intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);  in ivb_manual_fdi_link_train()
695 		intel_de_posting_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
700 			temp = intel_de_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
701 			drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);  in ivb_manual_fdi_link_train()
704 			    (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {  in ivb_manual_fdi_link_train()
705 				intel_de_write(dev_priv, reg,  in ivb_manual_fdi_link_train()
707 				drm_dbg_kms(&dev_priv->drm,  in ivb_manual_fdi_link_train()
715 			drm_dbg_kms(&dev_priv->drm,  in ivb_manual_fdi_link_train()
722 		temp = intel_de_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
725 		intel_de_write(dev_priv, reg, temp);  in ivb_manual_fdi_link_train()
728 		temp = intel_de_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
731 		intel_de_write(dev_priv, reg, temp);  in ivb_manual_fdi_link_train()
733 		intel_de_posting_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
738 			temp = intel_de_read(dev_priv, reg);  in ivb_manual_fdi_link_train()
739 			drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);  in ivb_manual_fdi_link_train()
742 			    (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {  in ivb_manual_fdi_link_train()
743 				intel_de_write(dev_priv, reg,  in ivb_manual_fdi_link_train()
745 				drm_dbg_kms(&dev_priv->drm,  in ivb_manual_fdi_link_train()
753 			drm_dbg_kms(&dev_priv->drm,  in ivb_manual_fdi_link_train()
758 	drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");  in ivb_manual_fdi_link_train()
773 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_fdi_link_train()  local
788 	intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),  in hsw_fdi_link_train()
792 	rx_ctl_val = dev_priv->display.fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |  in hsw_fdi_link_train()
795 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
796 	intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));  in hsw_fdi_link_train()
801 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
804 	drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);  in hsw_fdi_link_train()
811 		intel_de_write(dev_priv, DP_TP_CTL(PORT_E),  in hsw_fdi_link_train()
821 		intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),  in hsw_fdi_link_train()
823 		intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));  in hsw_fdi_link_train()
828 		intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));  in hsw_fdi_link_train()
832 		intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
833 		intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));  in hsw_fdi_link_train()
839 		temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
841 		intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);  in hsw_fdi_link_train()
842 		intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
847 		temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));  in hsw_fdi_link_train()
849 			drm_dbg_kms(&dev_priv->drm,  in hsw_fdi_link_train()
859 			drm_err(&dev_priv->drm, "FDI link training failed!\n");  in hsw_fdi_link_train()
864 		intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
865 		intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));  in hsw_fdi_link_train()
867 		temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));  in hsw_fdi_link_train()
869 		intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);  in hsw_fdi_link_train()
870 		intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));  in hsw_fdi_link_train()
873 		temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));  in hsw_fdi_link_train()
876 		intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);  in hsw_fdi_link_train()
877 		intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));  in hsw_fdi_link_train()
879 		intel_wait_ddi_buf_idle(dev_priv, PORT_E);  in hsw_fdi_link_train()
882 		temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
885 		intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);  in hsw_fdi_link_train()
886 		intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
890 	intel_de_write(dev_priv, DP_TP_CTL(PORT_E),  in hsw_fdi_link_train()
899 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in hsw_fdi_disable()  local
908 	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));  in hsw_fdi_disable()
910 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);  in hsw_fdi_disable()
912 	val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));  in hsw_fdi_disable()
914 	intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);  in hsw_fdi_disable()
916 	intel_wait_ddi_buf_idle(dev_priv, PORT_E);  in hsw_fdi_disable()
920 	val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));  in hsw_fdi_disable()
923 	intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);  in hsw_fdi_disable()
925 	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));  in hsw_fdi_disable()
927 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);  in hsw_fdi_disable()
929 	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));  in hsw_fdi_disable()
931 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);  in hsw_fdi_disable()
937 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_fdi_pll_enable()  local
944 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_pll_enable()
947 	temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;  in ilk_fdi_pll_enable()
948 	intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);  in ilk_fdi_pll_enable()
950 	intel_de_posting_read(dev_priv, reg);  in ilk_fdi_pll_enable()
954 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_pll_enable()
955 	intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);  in ilk_fdi_pll_enable()
957 	intel_de_posting_read(dev_priv, reg);  in ilk_fdi_pll_enable()
962 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_pll_enable()
964 		intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);  in ilk_fdi_pll_enable()
966 		intel_de_posting_read(dev_priv, reg);  in ilk_fdi_pll_enable()
974 	struct drm_i915_private *dev_priv = to_i915(dev);  in ilk_fdi_pll_disable()  local
981 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_pll_disable()
982 	intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);  in ilk_fdi_pll_disable()
986 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_pll_disable()
987 	intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);  in ilk_fdi_pll_disable()
989 	intel_de_posting_read(dev_priv, reg);  in ilk_fdi_pll_disable()
993 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_pll_disable()
994 	intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);  in ilk_fdi_pll_disable()
997 	intel_de_posting_read(dev_priv, reg);  in ilk_fdi_pll_disable()
1003 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_fdi_disable()  local
1010 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_disable()
1011 	intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);  in ilk_fdi_disable()
1012 	intel_de_posting_read(dev_priv, reg);  in ilk_fdi_disable()
1015 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_disable()
1017 	temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;  in ilk_fdi_disable()
1018 	intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);  in ilk_fdi_disable()
1020 	intel_de_posting_read(dev_priv, reg);  in ilk_fdi_disable()
1024 	if (HAS_PCH_IBX(dev_priv))  in ilk_fdi_disable()
1025 		intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),  in ilk_fdi_disable()
1030 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_disable()
1033 	intel_de_write(dev_priv, reg, temp);  in ilk_fdi_disable()
1036 	temp = intel_de_read(dev_priv, reg);  in ilk_fdi_disable()
1037 	if (HAS_PCH_CPT(dev_priv)) {  in ilk_fdi_disable()
1046 	temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;  in ilk_fdi_disable()
1047 	intel_de_write(dev_priv, reg, temp);  in ilk_fdi_disable()
1049 	intel_de_posting_read(dev_priv, reg);  in ilk_fdi_disable()
1066 intel_fdi_init_hook(struct drm_i915_private *dev_priv)  in intel_fdi_init_hook()  argument
1068 	if (IS_IRONLAKE(dev_priv)) {  in intel_fdi_init_hook()
1069 		dev_priv->display.funcs.fdi = &ilk_funcs;  in intel_fdi_init_hook()
1070 	} else if (IS_SANDYBRIDGE(dev_priv)) {  in intel_fdi_init_hook()
1071 		dev_priv->display.funcs.fdi = &gen6_funcs;  in intel_fdi_init_hook()
1072 	} else if (IS_IVYBRIDGE(dev_priv)) {  in intel_fdi_init_hook()
1074 		dev_priv->display.funcs.fdi = &ivb_funcs;  in intel_fdi_init_hook()