Lines Matching refs:dev_priv
51 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) in gen9_init_clock_gating() argument
53 if (HAS_LLC(dev_priv)) { in gen9_init_clock_gating()
61 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1, in gen9_init_clock_gating()
62 intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | in gen9_init_clock_gating()
67 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1, in gen9_init_clock_gating()
68 intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
71 intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, in gen9_init_clock_gating()
72 intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); in gen9_init_clock_gating()
78 …intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_… in gen9_init_clock_gating()
82 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) in bxt_init_clock_gating() argument
84 gen9_init_clock_gating(dev_priv); in bxt_init_clock_gating()
87 …intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGC… in bxt_init_clock_gating()
94 …intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGC… in bxt_init_clock_gating()
101 …intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN… in bxt_init_clock_gating()
110 intel_uncore_write(&dev_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950)); in bxt_init_clock_gating()
116 …intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_… in bxt_init_clock_gating()
123 intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), in bxt_init_clock_gating()
124 intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) | in bxt_init_clock_gating()
128 static void glk_init_clock_gating(struct drm_i915_private *dev_priv) in glk_init_clock_gating() argument
130 gen9_init_clock_gating(dev_priv); in glk_init_clock_gating()
137 …intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN… in glk_init_clock_gating()
141 static void pnv_get_mem_freq(struct drm_i915_private *dev_priv) in pnv_get_mem_freq() argument
145 tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG); in pnv_get_mem_freq()
149 dev_priv->fsb_freq = 533; /* 133*4 */ in pnv_get_mem_freq()
152 dev_priv->fsb_freq = 800; /* 200*4 */ in pnv_get_mem_freq()
155 dev_priv->fsb_freq = 667; /* 167*4 */ in pnv_get_mem_freq()
158 dev_priv->fsb_freq = 400; /* 100*4 */ in pnv_get_mem_freq()
164 dev_priv->mem_freq = 533; in pnv_get_mem_freq()
167 dev_priv->mem_freq = 667; in pnv_get_mem_freq()
170 dev_priv->mem_freq = 800; in pnv_get_mem_freq()
175 tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL); in pnv_get_mem_freq()
176 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; in pnv_get_mem_freq()
179 static void ilk_get_mem_freq(struct drm_i915_private *dev_priv) in ilk_get_mem_freq() argument
183 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); in ilk_get_mem_freq()
184 csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0); in ilk_get_mem_freq()
188 dev_priv->mem_freq = 800; in ilk_get_mem_freq()
191 dev_priv->mem_freq = 1066; in ilk_get_mem_freq()
194 dev_priv->mem_freq = 1333; in ilk_get_mem_freq()
197 dev_priv->mem_freq = 1600; in ilk_get_mem_freq()
200 drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n", in ilk_get_mem_freq()
202 dev_priv->mem_freq = 0; in ilk_get_mem_freq()
208 dev_priv->fsb_freq = 3200; in ilk_get_mem_freq()
211 dev_priv->fsb_freq = 3733; in ilk_get_mem_freq()
214 dev_priv->fsb_freq = 4266; in ilk_get_mem_freq()
217 dev_priv->fsb_freq = 4800; in ilk_get_mem_freq()
220 dev_priv->fsb_freq = 5333; in ilk_get_mem_freq()
223 dev_priv->fsb_freq = 5866; in ilk_get_mem_freq()
226 dev_priv->fsb_freq = 6400; in ilk_get_mem_freq()
229 drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", in ilk_get_mem_freq()
231 dev_priv->fsb_freq = 0; in ilk_get_mem_freq()
298 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) in chv_set_memory_dvfs() argument
302 vlv_punit_get(dev_priv); in chv_set_memory_dvfs()
304 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in chv_set_memory_dvfs()
311 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); in chv_set_memory_dvfs()
313 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in chv_set_memory_dvfs()
315 drm_err(&dev_priv->drm, in chv_set_memory_dvfs()
318 vlv_punit_put(dev_priv); in chv_set_memory_dvfs()
321 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) in chv_set_memory_pm5() argument
325 vlv_punit_get(dev_priv); in chv_set_memory_pm5()
327 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_memory_pm5()
332 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in chv_set_memory_pm5()
334 vlv_punit_put(dev_priv); in chv_set_memory_pm5()
340 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) in _intel_set_memory_cxsr() argument
345 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in _intel_set_memory_cxsr()
346 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; in _intel_set_memory_cxsr()
347 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); in _intel_set_memory_cxsr()
348 intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF_VLV); in _intel_set_memory_cxsr()
349 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) { in _intel_set_memory_cxsr()
350 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
351 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in _intel_set_memory_cxsr()
352 intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF); in _intel_set_memory_cxsr()
353 } else if (IS_PINEVIEW(dev_priv)) { in _intel_set_memory_cxsr()
354 val = intel_uncore_read(&dev_priv->uncore, DSPFW3); in _intel_set_memory_cxsr()
360 intel_uncore_write(&dev_priv->uncore, DSPFW3, val); in _intel_set_memory_cxsr()
361 intel_uncore_posting_read(&dev_priv->uncore, DSPFW3); in _intel_set_memory_cxsr()
362 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) { in _intel_set_memory_cxsr()
363 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
366 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, val); in _intel_set_memory_cxsr()
367 intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF); in _intel_set_memory_cxsr()
368 } else if (IS_I915GM(dev_priv)) { in _intel_set_memory_cxsr()
374 was_enabled = intel_uncore_read(&dev_priv->uncore, INSTPM) & INSTPM_SELF_EN; in _intel_set_memory_cxsr()
377 intel_uncore_write(&dev_priv->uncore, INSTPM, val); in _intel_set_memory_cxsr()
378 intel_uncore_posting_read(&dev_priv->uncore, INSTPM); in _intel_set_memory_cxsr()
383 trace_intel_memory_cxsr(dev_priv, was_enabled, enable); in _intel_set_memory_cxsr()
385 drm_dbg_kms(&dev_priv->drm, "memory self-refresh is %s (was %s)\n", in _intel_set_memory_cxsr()
429 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) in intel_set_memory_cxsr() argument
433 mutex_lock(&dev_priv->display.wm.wm_mutex); in intel_set_memory_cxsr()
434 ret = _intel_set_memory_cxsr(dev_priv, enable); in intel_set_memory_cxsr()
435 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_set_memory_cxsr()
436 dev_priv->display.wm.vlv.cxsr = enable; in intel_set_memory_cxsr()
437 else if (IS_G4X(dev_priv)) in intel_set_memory_cxsr()
438 dev_priv->display.wm.g4x.cxsr = enable; in intel_set_memory_cxsr()
439 mutex_unlock(&dev_priv->display.wm.wm_mutex); in intel_set_memory_cxsr()
466 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_get_fifo_size() local
474 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); in vlv_get_fifo_size()
475 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2); in vlv_get_fifo_size()
480 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); in vlv_get_fifo_size()
481 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2); in vlv_get_fifo_size()
486 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2); in vlv_get_fifo_size()
487 dsparb3 = intel_uncore_read(&dev_priv->uncore, DSPARB3); in vlv_get_fifo_size()
502 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, in i9xx_get_fifo_size() argument
505 u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); in i9xx_get_fifo_size()
512 drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n", in i9xx_get_fifo_size()
518 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, in i830_get_fifo_size() argument
521 u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); in i830_get_fifo_size()
529 drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n", in i830_get_fifo_size()
535 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, in i845_get_fifo_size() argument
538 u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); in i845_get_fifo_size()
544 drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n", in i845_get_fifo_size()
797 static int intel_wm_num_levels(struct drm_i915_private *dev_priv) in intel_wm_num_levels() argument
799 return dev_priv->display.wm.max_level + 1; in intel_wm_num_levels()
844 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv) in single_enabled_crtc() argument
848 for_each_intel_crtc(&dev_priv->drm, crtc) { in single_enabled_crtc()
859 static void pnv_update_wm(struct drm_i915_private *dev_priv) in pnv_update_wm() argument
866 latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv), in pnv_update_wm()
867 dev_priv->is_ddr3, in pnv_update_wm()
868 dev_priv->fsb_freq, in pnv_update_wm()
869 dev_priv->mem_freq); in pnv_update_wm()
871 drm_dbg_kms(&dev_priv->drm, in pnv_update_wm()
873 intel_set_memory_cxsr(dev_priv, false); in pnv_update_wm()
877 crtc = single_enabled_crtc(dev_priv); in pnv_update_wm()
888 reg = intel_uncore_read(&dev_priv->uncore, DSPFW1); in pnv_update_wm()
891 intel_uncore_write(&dev_priv->uncore, DSPFW1, reg); in pnv_update_wm()
892 drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg); in pnv_update_wm()
898 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3); in pnv_update_wm()
901 intel_uncore_write(&dev_priv->uncore, DSPFW3, reg); in pnv_update_wm()
907 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3); in pnv_update_wm()
910 intel_uncore_write(&dev_priv->uncore, DSPFW3, reg); in pnv_update_wm()
916 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3); in pnv_update_wm()
919 intel_uncore_write(&dev_priv->uncore, DSPFW3, reg); in pnv_update_wm()
920 drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg); in pnv_update_wm()
922 intel_set_memory_cxsr(dev_priv, true); in pnv_update_wm()
924 intel_set_memory_cxsr(dev_priv, false); in pnv_update_wm()
945 static void g4x_write_wm_values(struct drm_i915_private *dev_priv, in g4x_write_wm_values() argument
950 for_each_pipe(dev_priv, pipe) in g4x_write_wm_values()
951 trace_g4x_wm(intel_crtc_for_pipe(dev_priv, pipe), wm); in g4x_write_wm_values()
953 intel_uncore_write(&dev_priv->uncore, DSPFW1, in g4x_write_wm_values()
958 intel_uncore_write(&dev_priv->uncore, DSPFW2, in g4x_write_wm_values()
965 intel_uncore_write(&dev_priv->uncore, DSPFW3, in g4x_write_wm_values()
971 intel_uncore_posting_read(&dev_priv->uncore, DSPFW1); in g4x_write_wm_values()
977 static void vlv_write_wm_values(struct drm_i915_private *dev_priv, in vlv_write_wm_values() argument
982 for_each_pipe(dev_priv, pipe) { in vlv_write_wm_values()
983 trace_vlv_wm(intel_crtc_for_pipe(dev_priv, pipe), wm); in vlv_write_wm_values()
985 intel_uncore_write(&dev_priv->uncore, VLV_DDL(pipe), in vlv_write_wm_values()
997 intel_uncore_write(&dev_priv->uncore, DSPHOWM, 0); in vlv_write_wm_values()
998 intel_uncore_write(&dev_priv->uncore, DSPHOWM1, 0); in vlv_write_wm_values()
999 intel_uncore_write(&dev_priv->uncore, DSPFW4, 0); in vlv_write_wm_values()
1000 intel_uncore_write(&dev_priv->uncore, DSPFW5, 0); in vlv_write_wm_values()
1001 intel_uncore_write(&dev_priv->uncore, DSPFW6, 0); in vlv_write_wm_values()
1003 intel_uncore_write(&dev_priv->uncore, DSPFW1, in vlv_write_wm_values()
1008 intel_uncore_write(&dev_priv->uncore, DSPFW2, in vlv_write_wm_values()
1012 intel_uncore_write(&dev_priv->uncore, DSPFW3, in vlv_write_wm_values()
1015 if (IS_CHERRYVIEW(dev_priv)) { in vlv_write_wm_values()
1016 intel_uncore_write(&dev_priv->uncore, DSPFW7_CHV, in vlv_write_wm_values()
1019 intel_uncore_write(&dev_priv->uncore, DSPFW8_CHV, in vlv_write_wm_values()
1022 intel_uncore_write(&dev_priv->uncore, DSPFW9_CHV, in vlv_write_wm_values()
1025 intel_uncore_write(&dev_priv->uncore, DSPHOWM, in vlv_write_wm_values()
1037 intel_uncore_write(&dev_priv->uncore, DSPFW7, in vlv_write_wm_values()
1040 intel_uncore_write(&dev_priv->uncore, DSPHOWM, in vlv_write_wm_values()
1050 intel_uncore_posting_read(&dev_priv->uncore, DSPFW1); in vlv_write_wm_values()
1055 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv) in g4x_setup_wm_latency() argument
1058 dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5; in g4x_setup_wm_latency()
1059 dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_SR] = 12; in g4x_setup_wm_latency()
1060 dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35; in g4x_setup_wm_latency()
1062 dev_priv->display.wm.max_level = G4X_WM_LEVEL_HPLL; in g4x_setup_wm_latency()
1112 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in g4x_compute_wm() local
1115 unsigned int latency = dev_priv->display.wm.pri_latency[level] * 10; in g4x_compute_wm()
1166 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in g4x_raw_plane_wm_set() local
1169 for (; level < intel_wm_num_levels(dev_priv); level++) { in g4x_raw_plane_wm_set()
1182 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in g4x_raw_fbc_wm_set() local
1188 for (; level < intel_wm_num_levels(dev_priv); level++) { in g4x_raw_fbc_wm_set()
1206 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in g4x_raw_plane_wm_compute() local
1259 drm_dbg_kms(&dev_priv->drm, in g4x_raw_plane_wm_compute()
1267 drm_dbg_kms(&dev_priv->drm, in g4x_raw_plane_wm_compute()
1287 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in g4x_raw_crtc_wm_is_valid() local
1289 if (level > dev_priv->display.wm.max_level) in g4x_raw_crtc_wm_is_valid()
1423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in g4x_compute_intermediate_wm() local
1453 drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] > in g4x_compute_intermediate_wm()
1471 drm_WARN_ON(&dev_priv->drm, in g4x_compute_intermediate_wm()
1477 drm_WARN_ON(&dev_priv->drm, in g4x_compute_intermediate_wm()
1484 drm_WARN_ON(&dev_priv->drm, in g4x_compute_intermediate_wm()
1487 drm_WARN_ON(&dev_priv->drm, in g4x_compute_intermediate_wm()
1502 static void g4x_merge_wm(struct drm_i915_private *dev_priv, in g4x_merge_wm() argument
1512 for_each_intel_crtc(&dev_priv->drm, crtc) { in g4x_merge_wm()
1534 for_each_intel_crtc(&dev_priv->drm, crtc) { in g4x_merge_wm()
1546 static void g4x_program_watermarks(struct drm_i915_private *dev_priv) in g4x_program_watermarks() argument
1548 struct g4x_wm_values *old_wm = &dev_priv->display.wm.g4x; in g4x_program_watermarks()
1551 g4x_merge_wm(dev_priv, &new_wm); in g4x_program_watermarks()
1557 _intel_set_memory_cxsr(dev_priv, false); in g4x_program_watermarks()
1559 g4x_write_wm_values(dev_priv, &new_wm); in g4x_program_watermarks()
1562 _intel_set_memory_cxsr(dev_priv, true); in g4x_program_watermarks()
1570 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in g4x_initial_watermarks() local
1574 mutex_lock(&dev_priv->display.wm.wm_mutex); in g4x_initial_watermarks()
1576 g4x_program_watermarks(dev_priv); in g4x_initial_watermarks()
1577 mutex_unlock(&dev_priv->display.wm.wm_mutex); in g4x_initial_watermarks()
1583 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in g4x_optimize_watermarks() local
1590 mutex_lock(&dev_priv->display.wm.wm_mutex); in g4x_optimize_watermarks()
1592 g4x_program_watermarks(dev_priv); in g4x_optimize_watermarks()
1593 mutex_unlock(&dev_priv->display.wm.wm_mutex); in g4x_optimize_watermarks()
1612 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv) in vlv_setup_wm_latency() argument
1615 dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; in vlv_setup_wm_latency()
1617 dev_priv->display.wm.max_level = VLV_WM_LEVEL_PM2; in vlv_setup_wm_latency()
1619 if (IS_CHERRYVIEW(dev_priv)) { in vlv_setup_wm_latency()
1620 dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; in vlv_setup_wm_latency()
1621 dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; in vlv_setup_wm_latency()
1623 dev_priv->display.wm.max_level = VLV_WM_LEVEL_DDR_DVFS; in vlv_setup_wm_latency()
1632 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in vlv_compute_wm_level() local
1637 if (dev_priv->display.wm.pri_latency[level] == 0) in vlv_compute_wm_level()
1658 dev_priv->display.wm.pri_latency[level] * 10); in vlv_compute_wm_level()
1673 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_compute_fifo() local
1742 drm_WARN_ON(&dev_priv->drm, active_planes != 0 && fifo_left != 0); in vlv_compute_fifo()
1746 drm_WARN_ON(&dev_priv->drm, fifo_left != fifo_size); in vlv_compute_fifo()
1757 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_invalidate_wms() local
1759 for (; level < intel_wm_num_levels(dev_priv); level++) { in vlv_invalidate_wms()
1785 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in vlv_raw_plane_wm_set() local
1786 int num_levels = intel_wm_num_levels(dev_priv); in vlv_raw_plane_wm_set()
1803 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in vlv_raw_plane_wm_compute() local
1831 drm_dbg_kms(&dev_priv->drm, in vlv_raw_plane_wm_compute()
1863 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_compute_pipe_wm() local
1920 wm_state->num_levels = intel_wm_num_levels(dev_priv); in vlv_compute_pipe_wm()
1930 const int sr_fifo_size = INTEL_NUM_PIPES(dev_priv) * 512 - 1; in vlv_compute_pipe_wm()
1970 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_atomic_update_fifo() local
1971 struct intel_uncore *uncore = &dev_priv->uncore; in vlv_atomic_update_fifo()
1986 drm_WARN_ON(&dev_priv->drm, fifo_state->plane[PLANE_CURSOR] != 63); in vlv_atomic_update_fifo()
1987 drm_WARN_ON(&dev_priv->drm, fifo_size != 511); in vlv_atomic_update_fifo()
2117 static void vlv_merge_wm(struct drm_i915_private *dev_priv, in vlv_merge_wm() argument
2123 wm->level = dev_priv->display.wm.max_level; in vlv_merge_wm()
2126 for_each_intel_crtc(&dev_priv->drm, crtc) { in vlv_merge_wm()
2145 for_each_intel_crtc(&dev_priv->drm, crtc) { in vlv_merge_wm()
2160 static void vlv_program_watermarks(struct drm_i915_private *dev_priv) in vlv_program_watermarks() argument
2162 struct vlv_wm_values *old_wm = &dev_priv->display.wm.vlv; in vlv_program_watermarks()
2165 vlv_merge_wm(dev_priv, &new_wm); in vlv_program_watermarks()
2171 chv_set_memory_dvfs(dev_priv, false); in vlv_program_watermarks()
2174 chv_set_memory_pm5(dev_priv, false); in vlv_program_watermarks()
2177 _intel_set_memory_cxsr(dev_priv, false); in vlv_program_watermarks()
2179 vlv_write_wm_values(dev_priv, &new_wm); in vlv_program_watermarks()
2182 _intel_set_memory_cxsr(dev_priv, true); in vlv_program_watermarks()
2185 chv_set_memory_pm5(dev_priv, true); in vlv_program_watermarks()
2188 chv_set_memory_dvfs(dev_priv, true); in vlv_program_watermarks()
2196 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_initial_watermarks() local
2200 mutex_lock(&dev_priv->display.wm.wm_mutex); in vlv_initial_watermarks()
2202 vlv_program_watermarks(dev_priv); in vlv_initial_watermarks()
2203 mutex_unlock(&dev_priv->display.wm.wm_mutex); in vlv_initial_watermarks()
2209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_optimize_watermarks() local
2216 mutex_lock(&dev_priv->display.wm.wm_mutex); in vlv_optimize_watermarks()
2218 vlv_program_watermarks(dev_priv); in vlv_optimize_watermarks()
2219 mutex_unlock(&dev_priv->display.wm.wm_mutex); in vlv_optimize_watermarks()
2222 static void i965_update_wm(struct drm_i915_private *dev_priv) in i965_update_wm() argument
2230 crtc = single_enabled_crtc(dev_priv); in i965_update_wm()
2251 drm_dbg_kms(&dev_priv->drm, in i965_update_wm()
2266 drm_dbg_kms(&dev_priv->drm, in i965_update_wm()
2274 intel_set_memory_cxsr(dev_priv, false); in i965_update_wm()
2277 drm_dbg_kms(&dev_priv->drm, in i965_update_wm()
2282 intel_uncore_write(&dev_priv->uncore, DSPFW1, FW_WM(srwm, SR) | in i965_update_wm()
2286 intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) | in i965_update_wm()
2289 intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); in i965_update_wm()
2292 intel_set_memory_cxsr(dev_priv, true); in i965_update_wm()
2311 static void i9xx_update_wm(struct drm_i915_private *dev_priv) in i9xx_update_wm() argument
2321 if (IS_I945GM(dev_priv)) in i9xx_update_wm()
2323 else if (DISPLAY_VER(dev_priv) != 2) in i9xx_update_wm()
2328 if (DISPLAY_VER(dev_priv) == 2) in i9xx_update_wm()
2329 fifo_size = i830_get_fifo_size(dev_priv, PLANE_A); in i9xx_update_wm()
2331 fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A); in i9xx_update_wm()
2332 crtc = intel_crtc_for_plane(dev_priv, PLANE_A); in i9xx_update_wm()
2338 if (DISPLAY_VER(dev_priv) == 2) in i9xx_update_wm()
2352 if (DISPLAY_VER(dev_priv) == 2) in i9xx_update_wm()
2355 if (DISPLAY_VER(dev_priv) == 2) in i9xx_update_wm()
2356 fifo_size = i830_get_fifo_size(dev_priv, PLANE_B); in i9xx_update_wm()
2358 fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B); in i9xx_update_wm()
2359 crtc = intel_crtc_for_plane(dev_priv, PLANE_B); in i9xx_update_wm()
2365 if (DISPLAY_VER(dev_priv) == 2) in i9xx_update_wm()
2379 drm_dbg_kms(&dev_priv->drm, in i9xx_update_wm()
2382 crtc = single_enabled_crtc(dev_priv); in i9xx_update_wm()
2383 if (IS_I915GM(dev_priv) && crtc) { in i9xx_update_wm()
2399 intel_set_memory_cxsr(dev_priv, false); in i9xx_update_wm()
2402 if (HAS_FW_BLC(dev_priv) && crtc) { in i9xx_update_wm()
2415 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) in i9xx_update_wm()
2423 drm_dbg_kms(&dev_priv->drm, in i9xx_update_wm()
2429 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) in i9xx_update_wm()
2430 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, in i9xx_update_wm()
2433 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, srwm & 0x3f); in i9xx_update_wm()
2436 drm_dbg_kms(&dev_priv->drm, in i9xx_update_wm()
2447 intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo); in i9xx_update_wm()
2448 intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi); in i9xx_update_wm()
2451 intel_set_memory_cxsr(dev_priv, true); in i9xx_update_wm()
2454 static void i845_update_wm(struct drm_i915_private *dev_priv) in i845_update_wm() argument
2460 crtc = single_enabled_crtc(dev_priv); in i845_update_wm()
2466 i845_get_fifo_size(dev_priv, PLANE_A), in i845_update_wm()
2468 fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff; in i845_update_wm()
2471 drm_dbg_kms(&dev_priv->drm, in i845_update_wm()
2474 intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo); in i845_update_wm()
2629 ilk_display_fifo_size(const struct drm_i915_private *dev_priv) in ilk_display_fifo_size() argument
2631 if (DISPLAY_VER(dev_priv) >= 8) in ilk_display_fifo_size()
2633 else if (DISPLAY_VER(dev_priv) >= 7) in ilk_display_fifo_size()
2640 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, in ilk_plane_wm_reg_max() argument
2643 if (DISPLAY_VER(dev_priv) >= 8) in ilk_plane_wm_reg_max()
2646 else if (DISPLAY_VER(dev_priv) >= 7) in ilk_plane_wm_reg_max()
2658 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) in ilk_cursor_wm_reg_max() argument
2660 if (DISPLAY_VER(dev_priv) >= 7) in ilk_cursor_wm_reg_max()
2666 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) in ilk_fbc_wm_reg_max() argument
2668 if (DISPLAY_VER(dev_priv) >= 8) in ilk_fbc_wm_reg_max()
2675 static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv, in ilk_plane_wm_max() argument
2681 unsigned int fifo_size = ilk_display_fifo_size(dev_priv); in ilk_plane_wm_max()
2689 fifo_size /= INTEL_NUM_PIPES(dev_priv); in ilk_plane_wm_max()
2696 if (DISPLAY_VER(dev_priv) <= 6) in ilk_plane_wm_max()
2712 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite)); in ilk_plane_wm_max()
2716 static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv, in ilk_cursor_wm_max() argument
2725 return ilk_cursor_wm_reg_max(dev_priv, level); in ilk_cursor_wm_max()
2728 static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv, in ilk_compute_wm_maximums() argument
2734 max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false); in ilk_compute_wm_maximums()
2735 max->spr = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, true); in ilk_compute_wm_maximums()
2736 max->cur = ilk_cursor_wm_max(dev_priv, level, config); in ilk_compute_wm_maximums()
2737 max->fbc = ilk_fbc_wm_reg_max(dev_priv); in ilk_compute_wm_maximums()
2740 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv, in ilk_compute_wm_reg_maximums() argument
2744 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false); in ilk_compute_wm_reg_maximums()
2745 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true); in ilk_compute_wm_reg_maximums()
2746 max->cur = ilk_cursor_wm_reg_max(dev_priv, level); in ilk_compute_wm_reg_maximums()
2747 max->fbc = ilk_fbc_wm_reg_max(dev_priv); in ilk_compute_wm_reg_maximums()
2791 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, in ilk_compute_wm_level() argument
2800 u16 pri_latency = dev_priv->display.wm.pri_latency[level]; in ilk_compute_wm_level()
2801 u16 spr_latency = dev_priv->display.wm.spr_latency[level]; in ilk_compute_wm_level()
2802 u16 cur_latency = dev_priv->display.wm.cur_latency[level]; in ilk_compute_wm_level()
2865 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv, in intel_fixup_spr_wm_latency() argument
2869 if (DISPLAY_VER(dev_priv) == 5) in intel_fixup_spr_wm_latency()
2873 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv, in intel_fixup_cur_wm_latency() argument
2877 if (DISPLAY_VER(dev_priv) == 5) in intel_fixup_cur_wm_latency()
2881 int ilk_wm_max_level(const struct drm_i915_private *dev_priv) in ilk_wm_max_level() argument
2884 if (HAS_HW_SAGV_WM(dev_priv)) in ilk_wm_max_level()
2886 else if (DISPLAY_VER(dev_priv) >= 9) in ilk_wm_max_level()
2888 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in ilk_wm_max_level()
2890 else if (DISPLAY_VER(dev_priv) >= 6) in ilk_wm_max_level()
2896 void intel_print_wm_latency(struct drm_i915_private *dev_priv, in intel_print_wm_latency() argument
2899 int level, max_level = ilk_wm_max_level(dev_priv); in intel_print_wm_latency()
2905 drm_dbg_kms(&dev_priv->drm, in intel_print_wm_latency()
2915 if (DISPLAY_VER(dev_priv) >= 9) in intel_print_wm_latency()
2920 drm_dbg_kms(&dev_priv->drm, in intel_print_wm_latency()
2926 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, in ilk_increase_wm_latency() argument
2929 int level, max_level = ilk_wm_max_level(dev_priv); in ilk_increase_wm_latency()
2941 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv) in snb_wm_latency_quirk() argument
2949 changed = ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.pri_latency, 12); in snb_wm_latency_quirk()
2950 changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.spr_latency, 12); in snb_wm_latency_quirk()
2951 changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.cur_latency, 12); in snb_wm_latency_quirk()
2956 drm_dbg_kms(&dev_priv->drm, in snb_wm_latency_quirk()
2958 intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency); in snb_wm_latency_quirk()
2959 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency); in snb_wm_latency_quirk()
2960 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency); in snb_wm_latency_quirk()
2963 static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv) in snb_wm_lp3_irq_quirk() argument
2976 if (dev_priv->display.wm.pri_latency[3] == 0 && in snb_wm_lp3_irq_quirk()
2977 dev_priv->display.wm.spr_latency[3] == 0 && in snb_wm_lp3_irq_quirk()
2978 dev_priv->display.wm.cur_latency[3] == 0) in snb_wm_lp3_irq_quirk()
2981 dev_priv->display.wm.pri_latency[3] = 0; in snb_wm_lp3_irq_quirk()
2982 dev_priv->display.wm.spr_latency[3] = 0; in snb_wm_lp3_irq_quirk()
2983 dev_priv->display.wm.cur_latency[3] = 0; in snb_wm_lp3_irq_quirk()
2985 drm_dbg_kms(&dev_priv->drm, in snb_wm_lp3_irq_quirk()
2987 intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency); in snb_wm_lp3_irq_quirk()
2988 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency); in snb_wm_lp3_irq_quirk()
2989 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency); in snb_wm_lp3_irq_quirk()
2992 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) in ilk_setup_wm_latency() argument
2994 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in ilk_setup_wm_latency()
2995 hsw_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency); in ilk_setup_wm_latency()
2996 else if (DISPLAY_VER(dev_priv) >= 6) in ilk_setup_wm_latency()
2997 snb_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency); in ilk_setup_wm_latency()
2999 ilk_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency); in ilk_setup_wm_latency()
3001 memcpy(dev_priv->display.wm.spr_latency, dev_priv->display.wm.pri_latency, in ilk_setup_wm_latency()
3002 sizeof(dev_priv->display.wm.pri_latency)); in ilk_setup_wm_latency()
3003 memcpy(dev_priv->display.wm.cur_latency, dev_priv->display.wm.pri_latency, in ilk_setup_wm_latency()
3004 sizeof(dev_priv->display.wm.pri_latency)); in ilk_setup_wm_latency()
3006 intel_fixup_spr_wm_latency(dev_priv, dev_priv->display.wm.spr_latency); in ilk_setup_wm_latency()
3007 intel_fixup_cur_wm_latency(dev_priv, dev_priv->display.wm.cur_latency); in ilk_setup_wm_latency()
3009 intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency); in ilk_setup_wm_latency()
3010 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency); in ilk_setup_wm_latency()
3011 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency); in ilk_setup_wm_latency()
3013 if (DISPLAY_VER(dev_priv) == 6) { in ilk_setup_wm_latency()
3014 snb_wm_latency_quirk(dev_priv); in ilk_setup_wm_latency()
3015 snb_wm_lp3_irq_quirk(dev_priv); in ilk_setup_wm_latency()
3019 static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv, in ilk_validate_pipe_wm() argument
3031 ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max); in ilk_validate_pipe_wm()
3035 drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n"); in ilk_validate_pipe_wm()
3046 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in ilk_compute_pipe_wm() local
3055 int level, max_level = ilk_wm_max_level(dev_priv), usable_level; in ilk_compute_pipe_wm()
3076 if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled) in ilk_compute_pipe_wm()
3084 ilk_compute_wm_level(dev_priv, crtc, 0, crtc_state, in ilk_compute_pipe_wm()
3087 if (!ilk_validate_pipe_wm(dev_priv, pipe_wm)) in ilk_compute_pipe_wm()
3090 ilk_compute_wm_reg_maximums(dev_priv, 1, &max); in ilk_compute_pipe_wm()
3095 ilk_compute_wm_level(dev_priv, crtc, level, crtc_state, in ilk_compute_pipe_wm()
3120 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_compute_intermediate_wm() local
3127 int level, max_level = ilk_wm_max_level(dev_priv); in ilk_compute_intermediate_wm()
3161 if (!ilk_validate_pipe_wm(dev_priv, a)) in ilk_compute_intermediate_wm()
3177 static void ilk_merge_wm_level(struct drm_i915_private *dev_priv, in ilk_merge_wm_level() argument
3185 for_each_intel_crtc(&dev_priv->drm, crtc) { in ilk_merge_wm_level()
3210 static void ilk_wm_merge(struct drm_i915_private *dev_priv, in ilk_wm_merge() argument
3215 int level, max_level = ilk_wm_max_level(dev_priv); in ilk_wm_merge()
3219 if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) && in ilk_wm_merge()
3224 merged->fbc_wm_enabled = DISPLAY_VER(dev_priv) >= 6; in ilk_wm_merge()
3230 ilk_merge_wm_level(dev_priv, level, wm); in ilk_wm_merge()
3250 if (DISPLAY_VER(dev_priv) == 5 && HAS_FBC(dev_priv) && in ilk_wm_merge()
3251 dev_priv->params.enable_fbc && !merged->fbc_wm_enabled) { in ilk_wm_merge()
3267 static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv, in ilk_wm_lp_latency() argument
3270 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in ilk_wm_lp_latency()
3273 return dev_priv->display.wm.pri_latency[level]; in ilk_wm_lp_latency()
3276 static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, in ilk_compute_wm_results() argument
3300 WM_LP_LATENCY(ilk_wm_lp_latency(dev_priv, level)) | in ilk_compute_wm_results()
3307 if (DISPLAY_VER(dev_priv) >= 8) in ilk_compute_wm_results()
3318 if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) { in ilk_compute_wm_results()
3319 drm_WARN_ON(&dev_priv->drm, wm_lp != 1); in ilk_compute_wm_results()
3325 for_each_intel_crtc(&dev_priv->drm, crtc) { in ilk_compute_wm_results()
3330 if (drm_WARN_ON(&dev_priv->drm, !r->enable)) in ilk_compute_wm_results()
3343 ilk_find_best_result(struct drm_i915_private *dev_priv, in ilk_find_best_result() argument
3347 int level, max_level = ilk_wm_max_level(dev_priv); in ilk_find_best_result()
3376 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, in ilk_compute_wm_dirty() argument
3384 for_each_pipe(dev_priv, pipe) { in ilk_compute_wm_dirty()
3422 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, in _ilk_disable_lp_wm() argument
3425 struct ilk_wm_values *previous = &dev_priv->display.wm.hw; in _ilk_disable_lp_wm()
3430 intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]); in _ilk_disable_lp_wm()
3435 intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]); in _ilk_disable_lp_wm()
3440 intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]); in _ilk_disable_lp_wm()
3456 static void ilk_write_wm_values(struct drm_i915_private *dev_priv, in ilk_write_wm_values() argument
3459 struct ilk_wm_values *previous = &dev_priv->display.wm.hw; in ilk_write_wm_values()
3463 dirty = ilk_compute_wm_dirty(dev_priv, previous, results); in ilk_write_wm_values()
3467 _ilk_disable_lp_wm(dev_priv, dirty); in ilk_write_wm_values()
3470 intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]); in ilk_write_wm_values()
3472 intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]); in ilk_write_wm_values()
3474 intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]); in ilk_write_wm_values()
3477 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in ilk_write_wm_values()
3478 val = intel_uncore_read(&dev_priv->uncore, WM_MISC); in ilk_write_wm_values()
3483 intel_uncore_write(&dev_priv->uncore, WM_MISC, val); in ilk_write_wm_values()
3485 val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2); in ilk_write_wm_values()
3490 intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val); in ilk_write_wm_values()
3495 val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL); in ilk_write_wm_values()
3500 intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, val); in ilk_write_wm_values()
3505 intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK, results->wm_lp_spr[0]); in ilk_write_wm_values()
3507 if (DISPLAY_VER(dev_priv) >= 7) { in ilk_write_wm_values()
3509 intel_uncore_write(&dev_priv->uncore, WM2S_LP_IVB, results->wm_lp_spr[1]); in ilk_write_wm_values()
3511 intel_uncore_write(&dev_priv->uncore, WM3S_LP_IVB, results->wm_lp_spr[2]); in ilk_write_wm_values()
3515 intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, results->wm_lp[0]); in ilk_write_wm_values()
3517 intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, results->wm_lp[1]); in ilk_write_wm_values()
3519 intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, results->wm_lp[2]); in ilk_write_wm_values()
3521 dev_priv->display.wm.hw = *results; in ilk_write_wm_values()
3524 bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv) in ilk_disable_lp_wm() argument
3526 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); in ilk_disable_lp_wm()
3529 static void ilk_compute_wm_config(struct drm_i915_private *dev_priv, in ilk_compute_wm_config() argument
3535 for_each_intel_crtc(&dev_priv->drm, crtc) { in ilk_compute_wm_config()
3547 static void ilk_program_watermarks(struct drm_i915_private *dev_priv) in ilk_program_watermarks() argument
3555 ilk_compute_wm_config(dev_priv, &config); in ilk_program_watermarks()
3557 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max); in ilk_program_watermarks()
3558 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2); in ilk_program_watermarks()
3561 if (DISPLAY_VER(dev_priv) >= 7 && in ilk_program_watermarks()
3563 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max); in ilk_program_watermarks()
3564 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6); in ilk_program_watermarks()
3566 best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6); in ilk_program_watermarks()
3574 ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results); in ilk_program_watermarks()
3576 ilk_write_wm_values(dev_priv, &results); in ilk_program_watermarks()
3582 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_initial_watermarks() local
3586 mutex_lock(&dev_priv->display.wm.wm_mutex); in ilk_initial_watermarks()
3588 ilk_program_watermarks(dev_priv); in ilk_initial_watermarks()
3589 mutex_unlock(&dev_priv->display.wm.wm_mutex); in ilk_initial_watermarks()
3595 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_optimize_watermarks() local
3602 mutex_lock(&dev_priv->display.wm.wm_mutex); in ilk_optimize_watermarks()
3604 ilk_program_watermarks(dev_priv); in ilk_optimize_watermarks()
3605 mutex_unlock(&dev_priv->display.wm.wm_mutex); in ilk_optimize_watermarks()
3611 struct drm_i915_private *dev_priv = to_i915(dev); in ilk_pipe_wm_get_hw_state() local
3612 struct ilk_wm_values *hw = &dev_priv->display.wm.hw; in ilk_pipe_wm_get_hw_state()
3617 hw->wm_pipe[pipe] = intel_uncore_read(&dev_priv->uncore, WM0_PIPE_ILK(pipe)); in ilk_pipe_wm_get_hw_state()
3637 int level, max_level = ilk_wm_max_level(dev_priv); in ilk_pipe_wm_get_hw_state()
3656 static void g4x_read_wm_values(struct drm_i915_private *dev_priv, in g4x_read_wm_values() argument
3661 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1); in g4x_read_wm_values()
3667 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2); in g4x_read_wm_values()
3675 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3); in g4x_read_wm_values()
3682 static void vlv_read_wm_values(struct drm_i915_private *dev_priv, in vlv_read_wm_values() argument
3688 for_each_pipe(dev_priv, pipe) { in vlv_read_wm_values()
3689 tmp = intel_uncore_read(&dev_priv->uncore, VLV_DDL(pipe)); in vlv_read_wm_values()
3701 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1); in vlv_read_wm_values()
3707 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2); in vlv_read_wm_values()
3712 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3); in vlv_read_wm_values()
3715 if (IS_CHERRYVIEW(dev_priv)) { in vlv_read_wm_values()
3716 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7_CHV); in vlv_read_wm_values()
3720 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW8_CHV); in vlv_read_wm_values()
3724 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW9_CHV); in vlv_read_wm_values()
3728 tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM); in vlv_read_wm_values()
3740 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7); in vlv_read_wm_values()
3744 tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM); in vlv_read_wm_values()
3758 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv) in g4x_wm_get_hw_state() argument
3760 struct g4x_wm_values *wm = &dev_priv->display.wm.g4x; in g4x_wm_get_hw_state()
3763 g4x_read_wm_values(dev_priv, wm); in g4x_wm_get_hw_state()
3765 wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in g4x_wm_get_hw_state()
3767 for_each_intel_crtc(&dev_priv->drm, crtc) { in g4x_wm_get_hw_state()
3830 drm_dbg_kms(&dev_priv->drm, in g4x_wm_get_hw_state()
3838 drm_dbg_kms(&dev_priv->drm, in g4x_wm_get_hw_state()
3841 drm_dbg_kms(&dev_priv->drm, in g4x_wm_get_hw_state()
3844 drm_dbg_kms(&dev_priv->drm, "Initial SR=%s HPLL=%s FBC=%s\n", in g4x_wm_get_hw_state()
3849 void g4x_wm_sanitize(struct drm_i915_private *dev_priv) in g4x_wm_sanitize() argument
3854 mutex_lock(&dev_priv->display.wm.wm_mutex); in g4x_wm_sanitize()
3856 for_each_intel_plane(&dev_priv->drm, plane) { in g4x_wm_sanitize()
3858 intel_crtc_for_pipe(dev_priv, plane->pipe); in g4x_wm_sanitize()
3891 for_each_intel_crtc(&dev_priv->drm, crtc) { in g4x_wm_sanitize()
3900 g4x_program_watermarks(dev_priv); in g4x_wm_sanitize()
3902 mutex_unlock(&dev_priv->display.wm.wm_mutex); in g4x_wm_sanitize()
3905 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv) in vlv_wm_get_hw_state() argument
3907 struct vlv_wm_values *wm = &dev_priv->display.wm.vlv; in vlv_wm_get_hw_state()
3911 vlv_read_wm_values(dev_priv, wm); in vlv_wm_get_hw_state()
3913 wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; in vlv_wm_get_hw_state()
3916 if (IS_CHERRYVIEW(dev_priv)) { in vlv_wm_get_hw_state()
3917 vlv_punit_get(dev_priv); in vlv_wm_get_hw_state()
3919 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_wm_get_hw_state()
3932 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
3934 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); in vlv_wm_get_hw_state()
3936 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in vlv_wm_get_hw_state()
3938 drm_dbg_kms(&dev_priv->drm, in vlv_wm_get_hw_state()
3941 dev_priv->display.wm.max_level = VLV_WM_LEVEL_PM5; in vlv_wm_get_hw_state()
3943 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
3948 vlv_punit_put(dev_priv); in vlv_wm_get_hw_state()
3951 for_each_intel_crtc(&dev_priv->drm, crtc) { in vlv_wm_get_hw_state()
3991 drm_dbg_kms(&dev_priv->drm, in vlv_wm_get_hw_state()
4000 drm_dbg_kms(&dev_priv->drm, in vlv_wm_get_hw_state()
4005 void vlv_wm_sanitize(struct drm_i915_private *dev_priv) in vlv_wm_sanitize() argument
4010 mutex_lock(&dev_priv->display.wm.wm_mutex); in vlv_wm_sanitize()
4012 for_each_intel_plane(&dev_priv->drm, plane) { in vlv_wm_sanitize()
4014 intel_crtc_for_pipe(dev_priv, plane->pipe); in vlv_wm_sanitize()
4040 for_each_intel_crtc(&dev_priv->drm, crtc) { in vlv_wm_sanitize()
4049 vlv_program_watermarks(dev_priv); in vlv_wm_sanitize()
4051 mutex_unlock(&dev_priv->display.wm.wm_mutex); in vlv_wm_sanitize()
4058 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv) in ilk_init_lp_watermarks() argument
4060 …intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK)… in ilk_init_lp_watermarks()
4061 …intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK)… in ilk_init_lp_watermarks()
4062 …intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK)… in ilk_init_lp_watermarks()
4070 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv) in ilk_wm_get_hw_state() argument
4072 struct ilk_wm_values *hw = &dev_priv->display.wm.hw; in ilk_wm_get_hw_state()
4075 ilk_init_lp_watermarks(dev_priv); in ilk_wm_get_hw_state()
4077 for_each_intel_crtc(&dev_priv->drm, crtc) in ilk_wm_get_hw_state()
4080 hw->wm_lp[0] = intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK); in ilk_wm_get_hw_state()
4081 hw->wm_lp[1] = intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK); in ilk_wm_get_hw_state()
4082 hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK); in ilk_wm_get_hw_state()
4084 hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore, WM1S_LP_ILK); in ilk_wm_get_hw_state()
4085 if (DISPLAY_VER(dev_priv) >= 7) { in ilk_wm_get_hw_state()
4086 hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore, WM2S_LP_IVB); in ilk_wm_get_hw_state()
4087 hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore, WM3S_LP_IVB); in ilk_wm_get_hw_state()
4090 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in ilk_wm_get_hw_state()
4091 hw->partitioning = (intel_uncore_read(&dev_priv->uncore, WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? in ilk_wm_get_hw_state()
4093 else if (IS_IVYBRIDGE(dev_priv)) in ilk_wm_get_hw_state()
4094 …hw->partitioning = (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6)… in ilk_wm_get_hw_state()
4098 !(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS); in ilk_wm_get_hw_state()
4101 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv) in ibx_init_clock_gating() argument
4108 intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); in ibx_init_clock_gating()
4111 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) in g4x_disable_trickle_feed() argument
4115 for_each_pipe(dev_priv, pipe) { in g4x_disable_trickle_feed()
4116 intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe), in g4x_disable_trickle_feed()
4117 intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) | in g4x_disable_trickle_feed()
4120 …intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(… in g4x_disable_trickle_feed()
4121 intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe)); in g4x_disable_trickle_feed()
4125 static void ilk_init_clock_gating(struct drm_i915_private *dev_priv) in ilk_init_clock_gating() argument
4137 intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS0, in ilk_init_clock_gating()
4140 intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS1, in ilk_init_clock_gating()
4150 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, in ilk_init_clock_gating()
4151 (intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) | in ilk_init_clock_gating()
4154 intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, in ilk_init_clock_gating()
4155 (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) | in ilk_init_clock_gating()
4165 if (IS_IRONLAKE_M(dev_priv)) { in ilk_init_clock_gating()
4167 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1, in ilk_init_clock_gating()
4168 intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) | in ilk_init_clock_gating()
4170 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, in ilk_init_clock_gating()
4171 intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) | in ilk_init_clock_gating()
4175 intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); in ilk_init_clock_gating()
4177 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, in ilk_init_clock_gating()
4178 intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) | in ilk_init_clock_gating()
4181 g4x_disable_trickle_feed(dev_priv); in ilk_init_clock_gating()
4183 ibx_init_clock_gating(dev_priv); in ilk_init_clock_gating()
4186 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv) in cpt_init_clock_gating() argument
4196 intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | in cpt_init_clock_gating()
4199 …intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN2, intel_uncore_read(&dev_priv->uncore, SOUTH_C… in cpt_init_clock_gating()
4204 for_each_pipe(dev_priv, pipe) { in cpt_init_clock_gating()
4205 val = intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN2(pipe)); in cpt_init_clock_gating()
4208 if (dev_priv->display.vbt.fdi_rx_polarity_inverted) in cpt_init_clock_gating()
4212 intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN2(pipe), val); in cpt_init_clock_gating()
4215 for_each_pipe(dev_priv, pipe) { in cpt_init_clock_gating()
4216 intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(pipe), in cpt_init_clock_gating()
4221 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv) in gen6_check_mch_setup() argument
4225 tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD); in gen6_check_mch_setup()
4227 drm_dbg_kms(&dev_priv->drm, in gen6_check_mch_setup()
4232 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) in gen6_init_clock_gating() argument
4236 intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); in gen6_init_clock_gating()
4238 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
4239 intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) | in gen6_init_clock_gating()
4242 intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, in gen6_init_clock_gating()
4243 intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) | in gen6_init_clock_gating()
4260 intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2, in gen6_init_clock_gating()
4275 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1, in gen6_init_clock_gating()
4276 intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) | in gen6_init_clock_gating()
4278 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
4279 intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) | in gen6_init_clock_gating()
4281 intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, in gen6_init_clock_gating()
4282 intel_uncore_read(&dev_priv->uncore, ILK_DSPCLK_GATE_D) | in gen6_init_clock_gating()
4286 g4x_disable_trickle_feed(dev_priv); in gen6_init_clock_gating()
4288 cpt_init_clock_gating(dev_priv); in gen6_init_clock_gating()
4290 gen6_check_mch_setup(dev_priv); in gen6_init_clock_gating()
4293 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv) in lpt_init_clock_gating() argument
4299 if (HAS_PCH_LPT_LP(dev_priv)) in lpt_init_clock_gating()
4300 intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, in lpt_init_clock_gating()
4301 intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) | in lpt_init_clock_gating()
4305 intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A), in lpt_init_clock_gating()
4306 intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A)) | in lpt_init_clock_gating()
4310 static void lpt_suspend_hw(struct drm_i915_private *dev_priv) in lpt_suspend_hw() argument
4312 if (HAS_PCH_LPT_LP(dev_priv)) { in lpt_suspend_hw()
4313 u32 val = intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D); in lpt_suspend_hw()
4316 intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, val); in lpt_suspend_hw()
4320 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, in gen8_set_l3sqc_credits() argument
4328 misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL); in gen8_set_l3sqc_credits()
4329 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in gen8_set_l3sqc_credits()
4331 val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1); in gen8_set_l3sqc_credits()
4335 intel_uncore_write(&dev_priv->uncore, GEN8_L3SQCREG1, val); in gen8_set_l3sqc_credits()
4341 intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1); in gen8_set_l3sqc_credits()
4343 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); in gen8_set_l3sqc_credits()
4346 static void icl_init_clock_gating(struct drm_i915_private *dev_priv) in icl_init_clock_gating() argument
4349 intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), in icl_init_clock_gating()
4353 intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, in icl_init_clock_gating()
4357 static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) in gen12lp_init_clock_gating() argument
4360 if (DISPLAY_VER(dev_priv) == 12) in gen12lp_init_clock_gating()
4361 intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), in gen12lp_init_clock_gating()
4365 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) in gen12lp_init_clock_gating()
4366 …intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN… in gen12lp_init_clock_gating()
4370 if (DISPLAY_VER(dev_priv) == 12) in gen12lp_init_clock_gating()
4371 intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY, in gen12lp_init_clock_gating()
4375 static void adlp_init_clock_gating(struct drm_i915_private *dev_priv) in adlp_init_clock_gating() argument
4377 gen12lp_init_clock_gating(dev_priv); in adlp_init_clock_gating()
4380 intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); in adlp_init_clock_gating()
4383 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0); in adlp_init_clock_gating()
4386 static void dg1_init_clock_gating(struct drm_i915_private *dev_priv) in dg1_init_clock_gating() argument
4388 gen12lp_init_clock_gating(dev_priv); in dg1_init_clock_gating()
4391 if (IS_DG1_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0)) in dg1_init_clock_gating()
4392 …intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN… in dg1_init_clock_gating()
4396 static void xehpsdv_init_clock_gating(struct drm_i915_private *dev_priv) in xehpsdv_init_clock_gating() argument
4399 if (IS_XEHPSDV_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0)) in xehpsdv_init_clock_gating()
4400 intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS); in xehpsdv_init_clock_gating()
4418 static void pvc_init_clock_gating(struct drm_i915_private *dev_priv) in pvc_init_clock_gating() argument
4421 if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0)) in pvc_init_clock_gating()
4422 intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS); in pvc_init_clock_gating()
4425 if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0)) in pvc_init_clock_gating()
4426 intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); in pvc_init_clock_gating()
4429 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) in cnp_init_clock_gating() argument
4431 if (!HAS_PCH_CNP(dev_priv)) in cnp_init_clock_gating()
4435 …intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, intel_uncore_read(&dev_priv->uncore, SO… in cnp_init_clock_gating()
4439 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) in cfl_init_clock_gating() argument
4441 cnp_init_clock_gating(dev_priv); in cfl_init_clock_gating()
4442 gen9_init_clock_gating(dev_priv); in cfl_init_clock_gating()
4445 …intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_… in cfl_init_clock_gating()
4452 …intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_… in cfl_init_clock_gating()
4459 intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), in cfl_init_clock_gating()
4460 intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) | in cfl_init_clock_gating()
4464 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv) in kbl_init_clock_gating() argument
4466 gen9_init_clock_gating(dev_priv); in kbl_init_clock_gating()
4469 …intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_… in kbl_init_clock_gating()
4473 if (IS_KBL_GRAPHICS_STEP(dev_priv, 0, STEP_C0)) in kbl_init_clock_gating()
4474 …intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGC… in kbl_init_clock_gating()
4478 if (IS_KBL_GRAPHICS_STEP(dev_priv, 0, STEP_C0)) in kbl_init_clock_gating()
4479 …intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGC… in kbl_init_clock_gating()
4486 …intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_… in kbl_init_clock_gating()
4493 intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), in kbl_init_clock_gating()
4494 intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) | in kbl_init_clock_gating()
4498 static void skl_init_clock_gating(struct drm_i915_private *dev_priv) in skl_init_clock_gating() argument
4500 gen9_init_clock_gating(dev_priv); in skl_init_clock_gating()
4503 …intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MI… in skl_init_clock_gating()
4507 …intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_… in skl_init_clock_gating()
4514 …intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_… in skl_init_clock_gating()
4521 intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), in skl_init_clock_gating()
4522 intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) | in skl_init_clock_gating()
4529 intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), in skl_init_clock_gating()
4530 intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) | in skl_init_clock_gating()
4534 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) in bdw_init_clock_gating() argument
4539 intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A), in bdw_init_clock_gating()
4540 intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) | in bdw_init_clock_gating()
4544 …intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK)… in bdw_init_clock_gating()
4547 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1, in bdw_init_clock_gating()
4548 intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); in bdw_init_clock_gating()
4550 for_each_pipe(dev_priv, pipe) { in bdw_init_clock_gating()
4552 intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe), in bdw_init_clock_gating()
4553 intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe)) | in bdw_init_clock_gating()
4559 intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE, in bdw_init_clock_gating()
4560 intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) & in bdw_init_clock_gating()
4563 intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in bdw_init_clock_gating()
4567 …intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGC… in bdw_init_clock_gating()
4571 gen8_set_l3sqc_credits(dev_priv, 30, 2); in bdw_init_clock_gating()
4574 …intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR2_1, intel_uncore_read(&dev_priv->uncore, CHICKEN… in bdw_init_clock_gating()
4577 lpt_init_clock_gating(dev_priv); in bdw_init_clock_gating()
4584 intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, in bdw_init_clock_gating()
4585 intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); in bdw_init_clock_gating()
4588 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) in hsw_init_clock_gating() argument
4591 intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A), in hsw_init_clock_gating()
4592 intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) | in hsw_init_clock_gating()
4596 intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in hsw_init_clock_gating()
4597 intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | in hsw_init_clock_gating()
4601 …intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK)… in hsw_init_clock_gating()
4603 lpt_init_clock_gating(dev_priv); in hsw_init_clock_gating()
4606 static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) in ivb_init_clock_gating() argument
4610 intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); in ivb_init_clock_gating()
4613 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1, in ivb_init_clock_gating()
4614 intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) | in ivb_init_clock_gating()
4618 intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3, in ivb_init_clock_gating()
4622 if (IS_IVB_GT1(dev_priv)) in ivb_init_clock_gating()
4623 intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2, in ivb_init_clock_gating()
4627 intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2, in ivb_init_clock_gating()
4629 intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2_GT2, in ivb_init_clock_gating()
4637 intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2, in ivb_init_clock_gating()
4641 intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in ivb_init_clock_gating()
4642 intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | in ivb_init_clock_gating()
4645 g4x_disable_trickle_feed(dev_priv); in ivb_init_clock_gating()
4647 snpcr = intel_uncore_read(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR); in ivb_init_clock_gating()
4650 intel_uncore_write(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR, snpcr); in ivb_init_clock_gating()
4652 if (!HAS_PCH_NOP(dev_priv)) in ivb_init_clock_gating()
4653 cpt_init_clock_gating(dev_priv); in ivb_init_clock_gating()
4655 gen6_check_mch_setup(dev_priv); in ivb_init_clock_gating()
4658 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) in vlv_init_clock_gating() argument
4661 intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3, in vlv_init_clock_gating()
4666 intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2, in vlv_init_clock_gating()
4670 intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in vlv_init_clock_gating()
4671 intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | in vlv_init_clock_gating()
4678 intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2, in vlv_init_clock_gating()
4684 intel_uncore_write(&dev_priv->uncore, GEN7_UCGCTL4, in vlv_init_clock_gating()
4685 intel_uncore_read(&dev_priv->uncore, GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); in vlv_init_clock_gating()
4692 intel_uncore_write(&dev_priv->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS); in vlv_init_clock_gating()
4695 static void chv_init_clock_gating(struct drm_i915_private *dev_priv) in chv_init_clock_gating() argument
4699 intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE, in chv_init_clock_gating()
4700 intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) & in chv_init_clock_gating()
4704 intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in chv_init_clock_gating()
4708 …intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGC… in chv_init_clock_gating()
4712 …intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGC… in chv_init_clock_gating()
4720 gen8_set_l3sqc_credits(dev_priv, 38, 2); in chv_init_clock_gating()
4723 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) in g4x_init_clock_gating() argument
4727 intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, 0); in g4x_init_clock_gating()
4728 intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | in g4x_init_clock_gating()
4731 intel_uncore_write(&dev_priv->uncore, RAMCLK_GATE_D, 0); in g4x_init_clock_gating()
4735 if (IS_GM45(dev_priv)) in g4x_init_clock_gating()
4737 intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D(dev_priv), dspclk_gate); in g4x_init_clock_gating()
4739 g4x_disable_trickle_feed(dev_priv); in g4x_init_clock_gating()
4742 static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv) in i965gm_init_clock_gating() argument
4744 struct intel_uncore *uncore = &dev_priv->uncore; in i965gm_init_clock_gating()
4748 intel_uncore_write(uncore, DSPCLK_GATE_D(dev_priv), 0); in i965gm_init_clock_gating()
4756 static void i965g_init_clock_gating(struct drm_i915_private *dev_priv) in i965g_init_clock_gating() argument
4758 intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | in i965g_init_clock_gating()
4763 intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, 0); in i965g_init_clock_gating()
4764 intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, in i965g_init_clock_gating()
4768 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv) in gen3_init_clock_gating() argument
4770 u32 dstate = intel_uncore_read(&dev_priv->uncore, D_STATE); in gen3_init_clock_gating()
4774 intel_uncore_write(&dev_priv->uncore, D_STATE, dstate); in gen3_init_clock_gating()
4776 if (IS_PINEVIEW(dev_priv)) in gen3_init_clock_gating()
4777 intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE), in gen3_init_clock_gating()
4781 intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE), in gen3_init_clock_gating()
4785 intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); in gen3_init_clock_gating()
4788 intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); in gen3_init_clock_gating()
4790 intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, in gen3_init_clock_gating()
4794 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv) in i85x_init_clock_gating() argument
4796 intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); in i85x_init_clock_gating()
4799 intel_uncore_write(&dev_priv->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | in i85x_init_clock_gating()
4802 intel_uncore_write(&dev_priv->uncore, MEM_MODE, in i85x_init_clock_gating()
4812 intel_uncore_write(&dev_priv->uncore, SCPD0, in i85x_init_clock_gating()
4816 static void i830_init_clock_gating(struct drm_i915_private *dev_priv) in i830_init_clock_gating() argument
4818 intel_uncore_write(&dev_priv->uncore, MEM_MODE, in i830_init_clock_gating()
4823 void intel_init_clock_gating(struct drm_i915_private *dev_priv) in intel_init_clock_gating() argument
4825 dev_priv->clock_gating_funcs->init_clock_gating(dev_priv); in intel_init_clock_gating()
4828 void intel_suspend_hw(struct drm_i915_private *dev_priv) in intel_suspend_hw() argument
4830 if (HAS_PCH_LPT(dev_priv)) in intel_suspend_hw()
4831 lpt_suspend_hw(dev_priv); in intel_suspend_hw()
4834 static void nop_init_clock_gating(struct drm_i915_private *dev_priv) in nop_init_clock_gating() argument
4836 drm_dbg_kms(&dev_priv->drm, in nop_init_clock_gating()
4882 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) in intel_init_clock_gating_hooks() argument
4884 if (IS_PONTEVECCHIO(dev_priv)) in intel_init_clock_gating_hooks()
4885 dev_priv->clock_gating_funcs = &pvc_clock_gating_funcs; in intel_init_clock_gating_hooks()
4886 else if (IS_DG2(dev_priv)) in intel_init_clock_gating_hooks()
4887 dev_priv->clock_gating_funcs = &dg2_clock_gating_funcs; in intel_init_clock_gating_hooks()
4888 else if (IS_XEHPSDV(dev_priv)) in intel_init_clock_gating_hooks()
4889 dev_priv->clock_gating_funcs = &xehpsdv_clock_gating_funcs; in intel_init_clock_gating_hooks()
4890 else if (IS_ALDERLAKE_P(dev_priv)) in intel_init_clock_gating_hooks()
4891 dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs; in intel_init_clock_gating_hooks()
4892 else if (IS_DG1(dev_priv)) in intel_init_clock_gating_hooks()
4893 dev_priv->clock_gating_funcs = &dg1_clock_gating_funcs; in intel_init_clock_gating_hooks()
4894 else if (GRAPHICS_VER(dev_priv) == 12) in intel_init_clock_gating_hooks()
4895 dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs; in intel_init_clock_gating_hooks()
4896 else if (GRAPHICS_VER(dev_priv) == 11) in intel_init_clock_gating_hooks()
4897 dev_priv->clock_gating_funcs = &icl_clock_gating_funcs; in intel_init_clock_gating_hooks()
4898 else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) in intel_init_clock_gating_hooks()
4899 dev_priv->clock_gating_funcs = &cfl_clock_gating_funcs; in intel_init_clock_gating_hooks()
4900 else if (IS_SKYLAKE(dev_priv)) in intel_init_clock_gating_hooks()
4901 dev_priv->clock_gating_funcs = &skl_clock_gating_funcs; in intel_init_clock_gating_hooks()
4902 else if (IS_KABYLAKE(dev_priv)) in intel_init_clock_gating_hooks()
4903 dev_priv->clock_gating_funcs = &kbl_clock_gating_funcs; in intel_init_clock_gating_hooks()
4904 else if (IS_BROXTON(dev_priv)) in intel_init_clock_gating_hooks()
4905 dev_priv->clock_gating_funcs = &bxt_clock_gating_funcs; in intel_init_clock_gating_hooks()
4906 else if (IS_GEMINILAKE(dev_priv)) in intel_init_clock_gating_hooks()
4907 dev_priv->clock_gating_funcs = &glk_clock_gating_funcs; in intel_init_clock_gating_hooks()
4908 else if (IS_BROADWELL(dev_priv)) in intel_init_clock_gating_hooks()
4909 dev_priv->clock_gating_funcs = &bdw_clock_gating_funcs; in intel_init_clock_gating_hooks()
4910 else if (IS_CHERRYVIEW(dev_priv)) in intel_init_clock_gating_hooks()
4911 dev_priv->clock_gating_funcs = &chv_clock_gating_funcs; in intel_init_clock_gating_hooks()
4912 else if (IS_HASWELL(dev_priv)) in intel_init_clock_gating_hooks()
4913 dev_priv->clock_gating_funcs = &hsw_clock_gating_funcs; in intel_init_clock_gating_hooks()
4914 else if (IS_IVYBRIDGE(dev_priv)) in intel_init_clock_gating_hooks()
4915 dev_priv->clock_gating_funcs = &ivb_clock_gating_funcs; in intel_init_clock_gating_hooks()
4916 else if (IS_VALLEYVIEW(dev_priv)) in intel_init_clock_gating_hooks()
4917 dev_priv->clock_gating_funcs = &vlv_clock_gating_funcs; in intel_init_clock_gating_hooks()
4918 else if (GRAPHICS_VER(dev_priv) == 6) in intel_init_clock_gating_hooks()
4919 dev_priv->clock_gating_funcs = &gen6_clock_gating_funcs; in intel_init_clock_gating_hooks()
4920 else if (GRAPHICS_VER(dev_priv) == 5) in intel_init_clock_gating_hooks()
4921 dev_priv->clock_gating_funcs = &ilk_clock_gating_funcs; in intel_init_clock_gating_hooks()
4922 else if (IS_G4X(dev_priv)) in intel_init_clock_gating_hooks()
4923 dev_priv->clock_gating_funcs = &g4x_clock_gating_funcs; in intel_init_clock_gating_hooks()
4924 else if (IS_I965GM(dev_priv)) in intel_init_clock_gating_hooks()
4925 dev_priv->clock_gating_funcs = &i965gm_clock_gating_funcs; in intel_init_clock_gating_hooks()
4926 else if (IS_I965G(dev_priv)) in intel_init_clock_gating_hooks()
4927 dev_priv->clock_gating_funcs = &i965g_clock_gating_funcs; in intel_init_clock_gating_hooks()
4928 else if (GRAPHICS_VER(dev_priv) == 3) in intel_init_clock_gating_hooks()
4929 dev_priv->clock_gating_funcs = &gen3_clock_gating_funcs; in intel_init_clock_gating_hooks()
4930 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) in intel_init_clock_gating_hooks()
4931 dev_priv->clock_gating_funcs = &i85x_clock_gating_funcs; in intel_init_clock_gating_hooks()
4932 else if (GRAPHICS_VER(dev_priv) == 2) in intel_init_clock_gating_hooks()
4933 dev_priv->clock_gating_funcs = &i830_clock_gating_funcs; in intel_init_clock_gating_hooks()
4935 MISSING_CASE(INTEL_DEVID(dev_priv)); in intel_init_clock_gating_hooks()
4936 dev_priv->clock_gating_funcs = &nop_clock_gating_funcs; in intel_init_clock_gating_hooks()
4982 void intel_init_pm(struct drm_i915_private *dev_priv) in intel_init_pm() argument
4984 if (DISPLAY_VER(dev_priv) >= 9) { in intel_init_pm()
4985 skl_wm_init(dev_priv); in intel_init_pm()
4990 if (IS_PINEVIEW(dev_priv)) in intel_init_pm()
4991 pnv_get_mem_freq(dev_priv); in intel_init_pm()
4992 else if (GRAPHICS_VER(dev_priv) == 5) in intel_init_pm()
4993 ilk_get_mem_freq(dev_priv); in intel_init_pm()
4996 if (HAS_PCH_SPLIT(dev_priv)) { in intel_init_pm()
4997 ilk_setup_wm_latency(dev_priv); in intel_init_pm()
4999 if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->display.wm.pri_latency[1] && in intel_init_pm()
5000 dev_priv->display.wm.spr_latency[1] && dev_priv->display.wm.cur_latency[1]) || in intel_init_pm()
5001 (DISPLAY_VER(dev_priv) != 5 && dev_priv->display.wm.pri_latency[0] && in intel_init_pm()
5002 dev_priv->display.wm.spr_latency[0] && dev_priv->display.wm.cur_latency[0])) { in intel_init_pm()
5003 dev_priv->display.funcs.wm = &ilk_wm_funcs; in intel_init_pm()
5005 drm_dbg_kms(&dev_priv->drm, in intel_init_pm()
5008 dev_priv->display.funcs.wm = &nop_funcs; in intel_init_pm()
5010 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_init_pm()
5011 vlv_setup_wm_latency(dev_priv); in intel_init_pm()
5012 dev_priv->display.funcs.wm = &vlv_wm_funcs; in intel_init_pm()
5013 } else if (IS_G4X(dev_priv)) { in intel_init_pm()
5014 g4x_setup_wm_latency(dev_priv); in intel_init_pm()
5015 dev_priv->display.funcs.wm = &g4x_wm_funcs; in intel_init_pm()
5016 } else if (IS_PINEVIEW(dev_priv)) { in intel_init_pm()
5017 if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv), in intel_init_pm()
5018 dev_priv->is_ddr3, in intel_init_pm()
5019 dev_priv->fsb_freq, in intel_init_pm()
5020 dev_priv->mem_freq)) { in intel_init_pm()
5021 drm_info(&dev_priv->drm, in intel_init_pm()
5025 (dev_priv->is_ddr3 == 1) ? "3" : "2", in intel_init_pm()
5026 dev_priv->fsb_freq, dev_priv->mem_freq); in intel_init_pm()
5028 intel_set_memory_cxsr(dev_priv, false); in intel_init_pm()
5029 dev_priv->display.funcs.wm = &nop_funcs; in intel_init_pm()
5031 dev_priv->display.funcs.wm = &pnv_wm_funcs; in intel_init_pm()
5032 } else if (DISPLAY_VER(dev_priv) == 4) { in intel_init_pm()
5033 dev_priv->display.funcs.wm = &i965_wm_funcs; in intel_init_pm()
5034 } else if (DISPLAY_VER(dev_priv) == 3) { in intel_init_pm()
5035 dev_priv->display.funcs.wm = &i9xx_wm_funcs; in intel_init_pm()
5036 } else if (DISPLAY_VER(dev_priv) == 2) { in intel_init_pm()
5037 if (INTEL_NUM_PIPES(dev_priv) == 1) in intel_init_pm()
5038 dev_priv->display.funcs.wm = &i845_wm_funcs; in intel_init_pm()
5040 dev_priv->display.funcs.wm = &i9xx_wm_funcs; in intel_init_pm()
5042 drm_err(&dev_priv->drm, in intel_init_pm()
5044 dev_priv->display.funcs.wm = &nop_funcs; in intel_init_pm()
5048 void intel_pm_setup(struct drm_i915_private *dev_priv) in intel_pm_setup() argument
5050 dev_priv->runtime_pm.suspended = false; in intel_pm_setup()
5051 atomic_set(&dev_priv->runtime_pm.wakeref_count, 0); in intel_pm_setup()