462 #define INTEL_INFO(dev_priv)	(&(dev_priv)->__info)  argument
463 #define RUNTIME_INFO(dev_priv)	(&(dev_priv)->__runtime)  argument
464 #define DRIVER_CAPS(dev_priv)	(&(dev_priv)->caps)  argument
466 #define INTEL_DEVID(dev_priv)	(RUNTIME_INFO(dev_priv)->device_id)  argument
486 #define INTEL_REVID(dev_priv)	(to_pci_dev((dev_priv)->drm.dev)->revision)  argument
488 #define HAS_DSB(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dsb)  argument
573 #define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)  argument
574 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)  argument
576 #define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)  argument
577 #define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)  argument
578 #define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)  argument
579 #define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)  argument
580 #define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)  argument
581 #define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)  argument
582 #define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)  argument
583 #define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)  argument
584 #define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)  argument
585 #define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)  argument
586 #define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)  argument
587 #define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)  argument
588 #define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))  argument
589 #define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)  argument
590 #define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)  argument
591 #define IS_IRONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IRONLAKE)  argument
592 #define IS_IRONLAKE_M(dev_priv) \  argument
593 	(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
594 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)  argument
595 #define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)  argument
596 #define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \  argument
597 				 INTEL_INFO(dev_priv)->gt == 1)
598 #define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)  argument
599 #define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)  argument
600 #define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)  argument
601 #define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)  argument
602 #define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)  argument
603 #define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)  argument
604 #define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)  argument
605 #define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)  argument
606 #define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)  argument
607 #define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)  argument
608 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)  argument
609 #define IS_JSL_EHL(dev_priv)	(IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \  argument
610 				IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
611 #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)  argument
612 #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)  argument
613 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)  argument
614 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)  argument
615 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)  argument
616 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)  argument
617 #define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, INTEL_DG2)  argument
618 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)  argument
619 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)  argument
621 #define IS_METEORLAKE_M(dev_priv) \  argument
622 	IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
623 #define IS_METEORLAKE_P(dev_priv) \  argument
624 	IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
625 #define IS_DG2_G10(dev_priv) \  argument
626 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
627 #define IS_DG2_G11(dev_priv) \  argument
628 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
629 #define IS_DG2_G12(dev_priv) \  argument
630 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
631 #define IS_ADLS_RPLS(dev_priv) \  argument
632 	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
633 #define IS_ADLP_N(dev_priv) \  argument
634 	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
635 #define IS_ADLP_RPLP(dev_priv) \  argument
636 	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
637 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \  argument
638 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
639 #define IS_BDW_ULT(dev_priv) \  argument
640 	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
641 #define IS_BDW_ULX(dev_priv) \  argument
642 	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
643 #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \  argument
644 				 INTEL_INFO(dev_priv)->gt == 3)
645 #define IS_HSW_ULT(dev_priv) \  argument
646 	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
647 #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \  argument
648 				 INTEL_INFO(dev_priv)->gt == 3)
649 #define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \  argument
650 				 INTEL_INFO(dev_priv)->gt == 1)
652 #define IS_HSW_ULX(dev_priv) \  argument
653 	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
654 #define IS_SKL_ULT(dev_priv) \  argument
655 	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
656 #define IS_SKL_ULX(dev_priv) \  argument
657 	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
658 #define IS_KBL_ULT(dev_priv) \  argument
659 	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
660 #define IS_KBL_ULX(dev_priv) \  argument
661 	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
662 #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \  argument
663 				 INTEL_INFO(dev_priv)->gt == 2)
664 #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \  argument
665 				 INTEL_INFO(dev_priv)->gt == 3)
666 #define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \  argument
667 				 INTEL_INFO(dev_priv)->gt == 4)
668 #define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \  argument
669 				 INTEL_INFO(dev_priv)->gt == 2)
670 #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \  argument
671 				 INTEL_INFO(dev_priv)->gt == 3)
672 #define IS_CFL_ULT(dev_priv) \  argument
673 	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
674 #define IS_CFL_ULX(dev_priv) \  argument
675 	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
676 #define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \  argument
677 				 INTEL_INFO(dev_priv)->gt == 2)
678 #define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \  argument
679 				 INTEL_INFO(dev_priv)->gt == 3)
681 #define IS_CML_ULT(dev_priv) \  argument
682 	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
683 #define IS_CML_ULX(dev_priv) \  argument
684 	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
685 #define IS_CML_GT2(dev_priv)	(IS_COMETLAKE(dev_priv) && \  argument
686 				 INTEL_INFO(dev_priv)->gt == 2)
688 #define IS_ICL_WITH_PORT_F(dev_priv) \  argument
689 	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
691 #define IS_TGL_UY(dev_priv) \  argument
692 	IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
696 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \  argument
697 	(IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
698 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \  argument
699 	(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
776 #define IS_LP(dev_priv)		(INTEL_INFO(dev_priv)->is_lp)  argument
777 #define IS_GEN9_LP(dev_priv)	(GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))  argument
778 #define IS_GEN9_BC(dev_priv)	(GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))  argument
800 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)  argument
806 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)  argument
808 #define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)  argument
809 #define HAS_4TILE(dev_priv)	(INTEL_INFO(dev_priv)->has_4tile)  argument
810 #define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)  argument
811 #define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)  argument
812 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)  argument
813 #define HAS_WT(dev_priv)	HAS_EDRAM(dev_priv)  argument
815 #define HWS_NEEDS_PHYSICAL(dev_priv)	(INTEL_INFO(dev_priv)->hws_needs_physical)  argument
817 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \  argument
818 		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
819 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \  argument
820 		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
822 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)  argument
824 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)  argument
825 #define HAS_PPGTT(dev_priv) \  argument
826 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
827 #define HAS_FULL_PPGTT(dev_priv) \  argument
828 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
830 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \  argument
832 	((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
835 #define HAS_OVERLAY(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_overlay)  argument
836 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \  argument
837 		(INTEL_INFO(dev_priv)->display.overlay_needs_physical)
840 #define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))  argument
842 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)	\  argument
843 	(IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
846 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)			\  argument
847 	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
849 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)  argument
850 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \  argument
851 					IS_GEMINILAKE(dev_priv) || \
852 					IS_KABYLAKE(dev_priv))
857 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \  argument
858 					 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
859 #define SUPPORTS_TV(dev_priv)		(INTEL_INFO(dev_priv)->display.supports_tv)  argument
860 #define I915_HAS_HOTPLUG(dev_priv)	(INTEL_INFO(dev_priv)->display.has_hotplug)  argument
862 #define HAS_FW_BLC(dev_priv)	(DISPLAY_VER(dev_priv) > 2)  argument
863 #define HAS_FBC(dev_priv)	(RUNTIME_INFO(dev_priv)->fbc_mask != 0)  argument
864 #define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)  argument
866 #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))  argument
868 #define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dp_mst)  argument
869 #define HAS_DP20(dev_priv)	(IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)  argument
871 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)	(DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))  argument
873 #define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)  argument
874 #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)  argument
875 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)  argument
876 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)  argument
877 #define HAS_PSR_HW_TRACKING(dev_priv) \  argument
878 	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
879 #define HAS_PSR2_SEL_FETCH(dev_priv)	 (DISPLAY_VER(dev_priv) >= 12)  argument
880 #define HAS_TRANSCODER(dev_priv, trans)	 ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)…  argument
882 #define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)  argument
883 #define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)  argument
884 #define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */  argument
886 #define HAS_RPS(dev_priv)	(INTEL_INFO(dev_priv)->has_rps)  argument
888 #define HAS_DMC(dev_priv)	(RUNTIME_INFO(dev_priv)->has_dmc)  argument
890 #define HAS_HECI_PXP(dev_priv) \  argument
891 	(INTEL_INFO(dev_priv)->has_heci_pxp)
893 #define HAS_HECI_GSCFI(dev_priv) \  argument
894 	(INTEL_INFO(dev_priv)->has_heci_gscfi)
896 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))  argument
900 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)  argument
901 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)  argument
907 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)  argument
914 #define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)  argument
916 #define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ipc)  argument
921 #define HAS_EXTRA_GT_LIST(dev_priv)   (INTEL_INFO(dev_priv)->extra_gt_list)  argument
927 #define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)  argument
929 #define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)  argument
931 #define HAS_POOLED_EU(dev_priv)	(RUNTIME_INFO(dev_priv)->has_pooled_eu)  argument
933 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)  argument
935 #define HAS_PXP(dev_priv)  ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \  argument
936 			    INTEL_INFO(dev_priv)->has_pxp) && \
937 			    VDBOX_MASK(to_gt(dev_priv)))
939 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)  argument
941 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))  argument
946 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)  argument
947 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \  argument
948 				 2 : HAS_L3_DPF(dev_priv))
953 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))  argument
955 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)  argument
962 #define INTEL_DISPLAY_ENABLED(dev_priv) \  argument
963 	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),		\
964 	 !(dev_priv)->params.disable_display &&				\
965 	 !intel_opregion_headless_sku(dev_priv))
967 #define HAS_GUC_DEPRIVILEGE(dev_priv) \  argument
968 	(INTEL_INFO(dev_priv)->has_guc_deprivilege)
970 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \  argument
971 					      IS_ALDERLAKE_S(dev_priv))
981 mkwrite_device_info(struct drm_i915_private *dev_priv)  in mkwrite_device_info()  argument
983 	return (struct intel_device_info *)INTEL_INFO(dev_priv);  in mkwrite_device_info()