Lines Matching refs:dev_priv
88 struct drm_i915_private *dev_priv = to_i915(dev); in vlv_dsi_wait_for_fifo_empty() local
94 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), in vlv_dsi_wait_for_fifo_empty()
96 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
99 static void write_data(struct drm_i915_private *dev_priv, in write_data() argument
111 intel_de_write(dev_priv, reg, val); in write_data()
115 static void read_data(struct drm_i915_private *dev_priv, in read_data() argument
122 u32 val = intel_de_read(dev_priv, reg); in read_data()
134 struct drm_i915_private *dev_priv = to_i915(dev); in intel_dsi_host_transfer() local
163 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), in intel_dsi_host_transfer()
165 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
168 write_data(dev_priv, data_reg, packet.payload, in intel_dsi_host_transfer()
173 intel_de_write(dev_priv, MIPI_INTR_STAT(port), in intel_dsi_host_transfer()
177 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), in intel_dsi_host_transfer()
179 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
183 intel_de_write(dev_priv, ctrl_reg, in intel_dsi_host_transfer()
189 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), in intel_dsi_host_transfer()
191 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
194 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); in intel_dsi_host_transfer()
229 struct drm_i915_private *dev_priv = to_i915(dev); in dpi_send_cmd() local
239 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
242 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
243 drm_dbg_kms(&dev_priv->drm, in dpi_send_cmd()
246 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
249 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) in dpi_send_cmd()
250 drm_err(&dev_priv->drm, in dpi_send_cmd()
256 static void band_gap_reset(struct drm_i915_private *dev_priv) in band_gap_reset() argument
258 vlv_flisdsi_get(dev_priv); in band_gap_reset()
260 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); in band_gap_reset()
261 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); in band_gap_reset()
262 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); in band_gap_reset()
264 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); in band_gap_reset()
265 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); in band_gap_reset()
267 vlv_flisdsi_put(dev_priv); in band_gap_reset()
274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_compute_config() local
281 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_compute_config()
303 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_compute_config()
330 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enable_io() local
341 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
342 intel_de_write(dev_priv, MIPI_CTRL(port), in glk_dsi_enable_io()
347 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_enable_io()
349 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); in glk_dsi_enable_io()
353 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
354 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) in glk_dsi_enable_io()
358 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); in glk_dsi_enable_io()
363 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), in glk_dsi_enable_io()
365 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); in glk_dsi_enable_io()
371 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); in glk_dsi_enable_io()
379 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_device_ready() local
386 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), in glk_dsi_device_ready()
388 drm_err(&dev_priv->drm, "PHY is not ON\n"); in glk_dsi_device_ready()
392 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_device_ready()
393 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), in glk_dsi_device_ready()
398 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { in glk_dsi_device_ready()
399 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
402 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
406 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
409 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
412 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_device_ready()
414 drm_err(&dev_priv->drm, "ULPS not active\n"); in glk_dsi_device_ready()
417 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
420 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
423 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
426 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
428 val = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_device_ready()
430 intel_de_write(dev_priv, MIPI_CTRL(port), val); in glk_dsi_device_ready()
436 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), in glk_dsi_device_ready()
438 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
444 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), in glk_dsi_device_ready()
446 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
453 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_dsi_device_ready() local
458 drm_dbg_kms(&dev_priv->drm, "\n"); in bxt_dsi_device_ready()
462 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); in bxt_dsi_device_ready()
463 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port), in bxt_dsi_device_ready()
470 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in bxt_dsi_device_ready()
472 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in bxt_dsi_device_ready()
475 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in bxt_dsi_device_ready()
481 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_device_ready() local
486 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_device_ready()
488 vlv_flisdsi_get(dev_priv); in vlv_dsi_device_ready()
491 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); in vlv_dsi_device_ready()
492 vlv_flisdsi_put(dev_priv); in vlv_dsi_device_ready()
495 band_gap_reset(dev_priv); in vlv_dsi_device_ready()
499 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_device_ready()
507 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A)); in vlv_dsi_device_ready()
508 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A), in vlv_dsi_device_ready()
512 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_device_ready()
516 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_device_ready()
524 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_device_ready() local
526 if (IS_GEMINILAKE(dev_priv)) in intel_dsi_device_ready()
528 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_dsi_device_ready()
536 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enter_low_power_mode() local
543 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_enter_low_power_mode()
546 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_enter_low_power_mode()
551 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_enter_low_power_mode()
553 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_enter_low_power_mode()
558 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_enter_low_power_mode()
560 drm_err(&dev_priv->drm, in glk_dsi_enter_low_power_mode()
567 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_disable_mipi_io() local
573 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_disable_mipi_io()
575 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); in glk_dsi_disable_mipi_io()
579 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_disable_mipi_io()
581 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_disable_mipi_io()
586 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_disable_mipi_io()
588 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); in glk_dsi_disable_mipi_io()
600 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_clear_device_ready() local
604 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_clear_device_ready()
607 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in vlv_dsi_clear_device_ready()
611 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_clear_device_ready()
615 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_clear_device_ready()
619 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_clear_device_ready()
627 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) && in vlv_dsi_clear_device_ready()
628 intel_de_wait_for_clear(dev_priv, port_ctrl, in vlv_dsi_clear_device_ready()
630 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); in vlv_dsi_clear_device_ready()
633 val = intel_de_read(dev_priv, port_ctrl); in vlv_dsi_clear_device_ready()
634 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD); in vlv_dsi_clear_device_ready()
637 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); in vlv_dsi_clear_device_ready()
645 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_port_enable() local
652 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_port_enable()
654 temp = intel_de_read(dev_priv, in intel_dsi_port_enable()
659 intel_de_write(dev_priv, MIPI_CTRL(port), in intel_dsi_port_enable()
663 temp = intel_de_read(dev_priv, VLV_CHICKEN_3); in intel_dsi_port_enable()
667 intel_de_write(dev_priv, VLV_CHICKEN_3, temp); in intel_dsi_port_enable()
672 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in intel_dsi_port_enable()
676 temp = intel_de_read(dev_priv, port_ctrl); in intel_dsi_port_enable()
684 if (IS_BROXTON(dev_priv)) in intel_dsi_port_enable()
696 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); in intel_dsi_port_enable()
697 intel_de_posting_read(dev_priv, port_ctrl); in intel_dsi_port_enable()
704 struct drm_i915_private *dev_priv = to_i915(dev); in intel_dsi_port_disable() local
709 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in intel_dsi_port_disable()
714 temp = intel_de_read(dev_priv, port_ctrl); in intel_dsi_port_disable()
715 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE); in intel_dsi_port_disable()
716 intel_de_posting_read(dev_priv, port_ctrl); in intel_dsi_port_disable()
786 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsi_pre_enable() local
792 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_pre_enable()
796 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in intel_dsi_pre_enable()
802 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_pre_enable()
810 if (IS_BROXTON(dev_priv)) { in intel_dsi_pre_enable()
812 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); in intel_dsi_pre_enable()
813 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, in intel_dsi_pre_enable()
817 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); in intel_dsi_pre_enable()
818 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); in intel_dsi_pre_enable()
821 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dsi_pre_enable()
825 val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv)); in intel_dsi_pre_enable()
827 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val); in intel_dsi_pre_enable()
830 if (!IS_GEMINILAKE(dev_priv)) in intel_dsi_pre_enable()
849 if (IS_GEMINILAKE(dev_priv)) { in intel_dsi_pre_enable()
861 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) in intel_dsi_pre_enable()
873 intel_de_write(dev_priv, in intel_dsi_pre_enable()
935 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_clear_device_ready() local
937 if (IS_GEMINILAKE(dev_priv)) in intel_dsi_clear_device_ready()
948 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_post_disable() local
953 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_post_disable()
955 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
982 if (IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
984 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); in intel_dsi_post_disable()
985 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, in intel_dsi_post_disable()
989 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); in intel_dsi_post_disable()
990 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, in intel_dsi_post_disable()
994 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
1001 val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv)); in intel_dsi_post_disable()
1003 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val); in intel_dsi_post_disable()
1025 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_hw_state() local
1031 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_hw_state()
1033 wakeref = intel_display_power_get_if_enabled(dev_priv, in intel_dsi_get_hw_state()
1043 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in intel_dsi_get_hw_state()
1044 !bxt_dsi_pll_is_enabled(dev_priv)) in intel_dsi_get_hw_state()
1049 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in intel_dsi_get_hw_state()
1051 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; in intel_dsi_get_hw_state()
1058 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_get_hw_state()
1060 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
1064 u32 tmp = intel_de_read(dev_priv, in intel_dsi_get_hw_state()
1072 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) in intel_dsi_get_hw_state()
1075 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_get_hw_state()
1076 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in intel_dsi_get_hw_state()
1080 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
1093 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_dsi_get_hw_state()
1102 struct drm_i915_private *dev_priv = to_i915(dev); in bxt_dsi_get_pipe_config() local
1124 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) in bxt_dsi_get_pipe_config()
1128 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; in bxt_dsi_get_pipe_config()
1140 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
1143 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
1146 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
1150 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); in bxt_dsi_get_pipe_config()
1156 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); in bxt_dsi_get_pipe_config()
1157 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); in bxt_dsi_get_pipe_config()
1174 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); in bxt_dsi_get_pipe_config()
1175 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); in bxt_dsi_get_pipe_config()
1176 vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port)); in bxt_dsi_get_pipe_config()
1265 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_config() local
1269 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_config()
1273 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_get_config()
1306 struct drm_i915_private *dev_priv = to_i915(dev); in set_dsi_timings() local
1341 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in set_dsi_timings()
1348 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), in set_dsi_timings()
1350 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), in set_dsi_timings()
1352 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), in set_dsi_timings()
1356 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), in set_dsi_timings()
1358 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); in set_dsi_timings()
1362 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), in set_dsi_timings()
1364 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); in set_dsi_timings()
1367 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); in set_dsi_timings()
1368 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), in set_dsi_timings()
1370 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); in set_dsi_timings()
1396 struct drm_i915_private *dev_priv = to_i915(dev); in intel_dsi_prepare() local
1405 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); in intel_dsi_prepare()
1416 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dsi_prepare()
1421 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in intel_dsi_prepare()
1423 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), in intel_dsi_prepare()
1427 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in intel_dsi_prepare()
1429 intel_de_write(dev_priv, MIPI_CTRL(port), in intel_dsi_prepare()
1431 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_prepare()
1434 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in intel_dsi_prepare()
1438 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); in intel_dsi_prepare()
1442 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); in intel_dsi_prepare()
1443 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); in intel_dsi_prepare()
1445 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), in intel_dsi_prepare()
1448 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), in intel_dsi_prepare()
1469 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_prepare()
1476 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); in intel_dsi_prepare()
1497 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
1500 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
1503 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), in intel_dsi_prepare()
1505 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), in intel_dsi_prepare()
1507 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), in intel_dsi_prepare()
1513 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), in intel_dsi_prepare()
1516 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in intel_dsi_prepare()
1524 intel_de_write(dev_priv, in intel_dsi_prepare()
1530 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); in intel_dsi_prepare()
1533 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), in intel_dsi_prepare()
1541 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), in intel_dsi_prepare()
1550 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), in intel_dsi_prepare()
1553 if (IS_GEMINILAKE(dev_priv)) { in intel_dsi_prepare()
1554 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), in intel_dsi_prepare()
1557 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), in intel_dsi_prepare()
1566 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), in intel_dsi_prepare()
1569 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), in intel_dsi_prepare()
1597 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt); in intel_dsi_prepare()
1604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_unprepare() local
1609 if (IS_GEMINILAKE(dev_priv)) in intel_dsi_unprepare()
1614 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); in intel_dsi_unprepare()
1616 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_dsi_unprepare()
1620 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); in intel_dsi_unprepare()
1622 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)); in intel_dsi_unprepare()
1624 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); in intel_dsi_unprepare()
1626 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); in intel_dsi_unprepare()
1662 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in vlv_dsi_add_properties() local
1668 if (!HAS_GMCH(dev_priv)) in vlv_dsi_add_properties()
1692 struct drm_i915_private *dev_priv = to_i915(dev); in vlv_dphy_param_init() local
1741 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; in vlv_dphy_param_init()
1749 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", in vlv_dphy_param_init()
1770 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", in vlv_dphy_param_init()
1781 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", in vlv_dphy_param_init()
1791 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", in vlv_dphy_param_init()
1855 void vlv_dsi_init(struct drm_i915_private *dev_priv) in vlv_dsi_init() argument
1857 struct drm_device *dev = &dev_priv->drm; in vlv_dsi_init()
1867 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_init()
1870 if (!intel_bios_is_dsi_present(dev_priv, &port)) in vlv_dsi_init()
1873 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
1874 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE; in vlv_dsi_init()
1876 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE; in vlv_dsi_init()
1899 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
1919 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
1928 intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL); in vlv_dsi_init()
1935 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1938 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1954 drm_dbg_kms(&dev_priv->drm, "no device found\n"); in vlv_dsi_init()
1961 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", in vlv_dsi_init()
1965 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); in vlv_dsi_init()
1993 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); in vlv_dsi_init()