186 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)  in intel_hpd_init_pins()  argument
188 	struct intel_hotplug *hpd = &dev_priv->display.hotplug;  in intel_hpd_init_pins()
190 	if (HAS_GMCH(dev_priv)) {  in intel_hpd_init_pins()
191 		if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||  in intel_hpd_init_pins()
192 		    IS_CHERRYVIEW(dev_priv))  in intel_hpd_init_pins()
199 	if (DISPLAY_VER(dev_priv) >= 11)  in intel_hpd_init_pins()
201 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))  in intel_hpd_init_pins()
203 	else if (DISPLAY_VER(dev_priv) >= 8)  in intel_hpd_init_pins()
205 	else if (DISPLAY_VER(dev_priv) >= 7)  in intel_hpd_init_pins()
210 	if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&  in intel_hpd_init_pins()
211 	    (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))  in intel_hpd_init_pins()
214 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)  in intel_hpd_init_pins()
216 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in intel_hpd_init_pins()
218 	else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))  in intel_hpd_init_pins()
220 	else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))  in intel_hpd_init_pins()
222 	else if (HAS_PCH_IBX(dev_priv))  in intel_hpd_init_pins()
225 		MISSING_CASE(INTEL_PCH_TYPE(dev_priv));  in intel_hpd_init_pins()
229 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)  in intel_handle_vblank()  argument
231 	struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);  in intel_handle_vblank()
324 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,  in i915_hotplug_interrupt_update_locked()  argument
330 	lockdep_assert_held(&dev_priv->irq_lock);  in i915_hotplug_interrupt_update_locked()
331 	drm_WARN_ON(&dev_priv->drm, bits & ~mask);  in i915_hotplug_interrupt_update_locked()
333 	val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN);  in i915_hotplug_interrupt_update_locked()
336 	intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val);  in i915_hotplug_interrupt_update_locked()
351 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,  in i915_hotplug_interrupt_update()  argument
355 	spin_lock_irq(&dev_priv->irq_lock);  in i915_hotplug_interrupt_update()
356 	i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);  in i915_hotplug_interrupt_update()
357 	spin_unlock_irq(&dev_priv->irq_lock);  in i915_hotplug_interrupt_update()
366 static void ilk_update_display_irq(struct drm_i915_private *dev_priv,  in ilk_update_display_irq()  argument
371 	lockdep_assert_held(&dev_priv->irq_lock);  in ilk_update_display_irq()
372 	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);  in ilk_update_display_irq()
374 	new_val = dev_priv->irq_mask;  in ilk_update_display_irq()
378 	if (new_val != dev_priv->irq_mask &&  in ilk_update_display_irq()
379 	    !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {  in ilk_update_display_irq()
380 		dev_priv->irq_mask = new_val;  in ilk_update_display_irq()
381 		intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask);  in ilk_update_display_irq()
382 		intel_uncore_posting_read(&dev_priv->uncore, DEIMR);  in ilk_update_display_irq()
402 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,  in bdw_update_port_irq()  argument
409 	lockdep_assert_held(&dev_priv->irq_lock);  in bdw_update_port_irq()
411 	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);  in bdw_update_port_irq()
413 	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))  in bdw_update_port_irq()
416 	old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);  in bdw_update_port_irq()
423 		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val);  in bdw_update_port_irq()
424 		intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);  in bdw_update_port_irq()
435 static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,  in bdw_update_pipe_irq()  argument
441 	lockdep_assert_held(&dev_priv->irq_lock);  in bdw_update_pipe_irq()
443 	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);  in bdw_update_pipe_irq()
445 	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))  in bdw_update_pipe_irq()
448 	new_val = dev_priv->de_irq_mask[pipe];  in bdw_update_pipe_irq()
452 	if (new_val != dev_priv->de_irq_mask[pipe]) {  in bdw_update_pipe_irq()
453 		dev_priv->de_irq_mask[pipe] = new_val;  in bdw_update_pipe_irq()
454 		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);  in bdw_update_pipe_irq()
455 		intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe));  in bdw_update_pipe_irq()
477 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,  in ibx_display_interrupt_update()  argument
481 	u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR);  in ibx_display_interrupt_update()
485 	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);  in ibx_display_interrupt_update()
487 	lockdep_assert_held(&dev_priv->irq_lock);  in ibx_display_interrupt_update()
489 	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))  in ibx_display_interrupt_update()
492 	intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr);  in ibx_display_interrupt_update()
493 	intel_uncore_posting_read(&dev_priv->uncore, SDEIMR);  in ibx_display_interrupt_update()
506 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,  in i915_pipestat_enable_mask()  argument
509 	u32 status_mask = dev_priv->pipestat_irq_mask[pipe];  in i915_pipestat_enable_mask()
512 	lockdep_assert_held(&dev_priv->irq_lock);  in i915_pipestat_enable_mask()
514 	if (DISPLAY_VER(dev_priv) < 5)  in i915_pipestat_enable_mask()
521 	if (drm_WARN_ON_ONCE(&dev_priv->drm,  in i915_pipestat_enable_mask()
528 	if (drm_WARN_ON_ONCE(&dev_priv->drm,  in i915_pipestat_enable_mask()
541 	drm_WARN_ONCE(&dev_priv->drm,  in i915_pipestat_enable_mask()
550 void i915_enable_pipestat(struct drm_i915_private *dev_priv,  in i915_enable_pipestat()  argument
556 	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,  in i915_enable_pipestat()
560 	lockdep_assert_held(&dev_priv->irq_lock);  in i915_enable_pipestat()
561 	drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));  in i915_enable_pipestat()
563 	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)  in i915_enable_pipestat()
566 	dev_priv->pipestat_irq_mask[pipe] |= status_mask;  in i915_enable_pipestat()
567 	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);  in i915_enable_pipestat()
569 	intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);  in i915_enable_pipestat()
570 	intel_uncore_posting_read(&dev_priv->uncore, reg);  in i915_enable_pipestat()
573 void i915_disable_pipestat(struct drm_i915_private *dev_priv,  in i915_disable_pipestat()  argument
579 	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,  in i915_disable_pipestat()
583 	lockdep_assert_held(&dev_priv->irq_lock);  in i915_disable_pipestat()
584 	drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));  in i915_disable_pipestat()
586 	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)  in i915_disable_pipestat()
589 	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;  in i915_disable_pipestat()
590 	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);  in i915_disable_pipestat()
592 	intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);  in i915_disable_pipestat()
593 	intel_uncore_posting_read(&dev_priv->uncore, reg);  in i915_disable_pipestat()
596 static bool i915_has_asle(struct drm_i915_private *dev_priv)  in i915_has_asle()  argument
598 	if (!dev_priv->display.opregion.asle)  in i915_has_asle()
601 	return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);  in i915_has_asle()
608 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)  in i915_enable_asle_pipestat()  argument
610 	if (!i915_has_asle(dev_priv))  in i915_enable_asle_pipestat()
613 	spin_lock_irq(&dev_priv->irq_lock);  in i915_enable_asle_pipestat()
615 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);  in i915_enable_asle_pipestat()
616 	if (DISPLAY_VER(dev_priv) >= 4)  in i915_enable_asle_pipestat()
617 		i915_enable_pipestat(dev_priv, PIPE_A,  in i915_enable_asle_pipestat()
620 	spin_unlock_irq(&dev_priv->irq_lock);  in i915_enable_asle_pipestat()
678 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i915_get_vblank_counter()  local
679 	struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];  in i915_get_vblank_counter()
715 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);  in i915_get_vblank_counter()
723 		high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;  in i915_get_vblank_counter()
724 		low   = intel_de_read_fw(dev_priv, low_frame);  in i915_get_vblank_counter()
725 		high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;  in i915_get_vblank_counter()
728 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);  in i915_get_vblank_counter()
744 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in g4x_get_vblank_counter()  local
745 	struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];  in g4x_get_vblank_counter()
751 	return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));  in g4x_get_vblank_counter()
756 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_scanlines_since_frame_timestamp()  local
776 		scan_prev_time = intel_de_read_fw(dev_priv,  in intel_crtc_scanlines_since_frame_timestamp()
783 		scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);  in intel_crtc_scanlines_since_frame_timestamp()
785 		scan_post_time = intel_de_read_fw(dev_priv,  in intel_crtc_scanlines_since_frame_timestamp()
824 	struct drm_i915_private *dev_priv = to_i915(dev);  in __intel_get_crtc_scanline()  local
843 	position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;  in __intel_get_crtc_scanline()
857 	if (HAS_DDI(dev_priv) && !position) {  in __intel_get_crtc_scanline()
862 			temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;  in __intel_get_crtc_scanline()
884 	struct drm_i915_private *dev_priv = to_i915(dev);  in i915_get_crtc_scanoutpos()  local
890 	bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||  in i915_get_crtc_scanoutpos()
891 		IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||  in i915_get_crtc_scanoutpos()
894 	if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {  in i915_get_crtc_scanoutpos()
895 		drm_dbg(&dev_priv->drm,  in i915_get_crtc_scanoutpos()
918 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);  in i915_get_crtc_scanoutpos()
949 …position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIF…  in i915_get_crtc_scanoutpos()
986 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);  in i915_get_crtc_scanoutpos()
1020 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_get_crtc_scanline()  local
1024 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);  in intel_get_crtc_scanline()
1026 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);  in intel_get_crtc_scanline()
1042 	struct drm_i915_private *dev_priv =  in ivb_parity_work()  local
1043 		container_of(work, typeof(*dev_priv), l3_parity.error_work);  in ivb_parity_work()
1044 	struct intel_gt *gt = to_gt(dev_priv);  in ivb_parity_work()
1054 	mutex_lock(&dev_priv->drm.struct_mutex);  in ivb_parity_work()
1057 	if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))  in ivb_parity_work()
1060 	misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);  in ivb_parity_work()
1061 	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);  in ivb_parity_work()
1062 	intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);  in ivb_parity_work()
1064 	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {  in ivb_parity_work()
1068 		if (drm_WARN_ON_ONCE(&dev_priv->drm,  in ivb_parity_work()
1069 				     slice >= NUM_L3_SLICES(dev_priv)))  in ivb_parity_work()
1072 		dev_priv->l3_parity.which_slice &= ~(1<<slice);  in ivb_parity_work()
1076 		error_status = intel_uncore_read(&dev_priv->uncore, reg);  in ivb_parity_work()
1081 		intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);  in ivb_parity_work()
1082 		intel_uncore_posting_read(&dev_priv->uncore, reg);  in ivb_parity_work()
1091 		kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,  in ivb_parity_work()
1103 	intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);  in ivb_parity_work()
1106 	drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);  in ivb_parity_work()
1108 	gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));  in ivb_parity_work()
1111 	mutex_unlock(&dev_priv->drm.struct_mutex);  in ivb_parity_work()
1242 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,  in intel_get_hpd_pins()  argument
1262 	drm_dbg(&dev_priv->drm,  in intel_get_hpd_pins()
1268 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,  in intel_hpd_enabled_irqs()  argument
1274 	for_each_intel_encoder(&dev_priv->drm, encoder)  in intel_hpd_enabled_irqs()
1275 		if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)  in intel_hpd_enabled_irqs()
1281 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,  in intel_hpd_hotplug_irqs()  argument
1287 	for_each_intel_encoder(&dev_priv->drm, encoder)  in intel_hpd_hotplug_irqs()
1305 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)  in gmbus_irq_handler()  argument
1307 	wake_up_all(&dev_priv->display.gmbus.wait_queue);  in gmbus_irq_handler()
1310 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)  in dp_aux_irq_handler()  argument
1312 	wake_up_all(&dev_priv->display.gmbus.wait_queue);  in dp_aux_irq_handler()
1316 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,  in display_pipe_crc_irq_handler()  argument
1322 	struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);  in display_pipe_crc_irq_handler()
1338 	    (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) {  in display_pipe_crc_irq_handler()
1351 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,  in display_pipe_crc_irq_handler()  argument
1376 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,  in hsw_pipe_crc_irq_handler()  argument
1379 	display_pipe_crc_irq_handler(dev_priv, pipe,  in hsw_pipe_crc_irq_handler()
1380 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),  in hsw_pipe_crc_irq_handler()
1384 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,  in ivb_pipe_crc_irq_handler()  argument
1387 	display_pipe_crc_irq_handler(dev_priv, pipe,  in ivb_pipe_crc_irq_handler()
1388 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),  in ivb_pipe_crc_irq_handler()
1389 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),  in ivb_pipe_crc_irq_handler()
1390 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),  in ivb_pipe_crc_irq_handler()
1391 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),  in ivb_pipe_crc_irq_handler()
1392 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));  in ivb_pipe_crc_irq_handler()
1395 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,  in i9xx_pipe_crc_irq_handler()  argument
1400 	if (DISPLAY_VER(dev_priv) >= 3)  in i9xx_pipe_crc_irq_handler()
1401 		res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe));  in i9xx_pipe_crc_irq_handler()
1405 	if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))  in i9xx_pipe_crc_irq_handler()
1406 		res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe));  in i9xx_pipe_crc_irq_handler()
1410 	display_pipe_crc_irq_handler(dev_priv, pipe,  in i9xx_pipe_crc_irq_handler()
1411 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)),  in i9xx_pipe_crc_irq_handler()
1412 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)),  in i9xx_pipe_crc_irq_handler()
1413 				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)),  in i9xx_pipe_crc_irq_handler()
1417 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)  in i9xx_pipestat_irq_reset()  argument
1421 	for_each_pipe(dev_priv, pipe) {  in i9xx_pipestat_irq_reset()
1422 		intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe),  in i9xx_pipestat_irq_reset()
1426 		dev_priv->pipestat_irq_mask[pipe] = 0;  in i9xx_pipestat_irq_reset()
1430 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,  in i9xx_pipestat_irq_ack()  argument
1435 	spin_lock(&dev_priv->irq_lock);  in i9xx_pipestat_irq_ack()
1437 	if (!dev_priv->display_irqs_enabled) {  in i9xx_pipestat_irq_ack()
1438 		spin_unlock(&dev_priv->irq_lock);  in i9xx_pipestat_irq_ack()
1442 	for_each_pipe(dev_priv, pipe) {  in i9xx_pipestat_irq_ack()
1470 			status_mask |= dev_priv->pipestat_irq_mask[pipe];  in i9xx_pipestat_irq_ack()
1476 		pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;  in i9xx_pipestat_irq_ack()
1477 		enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);  in i9xx_pipestat_irq_ack()
1489 			intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]);  in i9xx_pipestat_irq_ack()
1490 			intel_uncore_write(&dev_priv->uncore, reg, enable_mask);  in i9xx_pipestat_irq_ack()
1493 	spin_unlock(&dev_priv->irq_lock);  in i9xx_pipestat_irq_ack()
1496 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,  in i8xx_pipestat_irq_handler()  argument
1501 	for_each_pipe(dev_priv, pipe) {  in i8xx_pipestat_irq_handler()
1503 			intel_handle_vblank(dev_priv, pipe);  in i8xx_pipestat_irq_handler()
1506 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);  in i8xx_pipestat_irq_handler()
1509 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in i8xx_pipestat_irq_handler()
1513 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,  in i915_pipestat_irq_handler()  argument
1519 	for_each_pipe(dev_priv, pipe) {  in i915_pipestat_irq_handler()
1521 			intel_handle_vblank(dev_priv, pipe);  in i915_pipestat_irq_handler()
1527 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);  in i915_pipestat_irq_handler()
1530 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in i915_pipestat_irq_handler()
1534 		intel_opregion_asle_intr(dev_priv);  in i915_pipestat_irq_handler()
1537 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,  in i965_pipestat_irq_handler()  argument
1543 	for_each_pipe(dev_priv, pipe) {  in i965_pipestat_irq_handler()
1545 			intel_handle_vblank(dev_priv, pipe);  in i965_pipestat_irq_handler()
1551 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);  in i965_pipestat_irq_handler()
1554 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in i965_pipestat_irq_handler()
1558 		intel_opregion_asle_intr(dev_priv);  in i965_pipestat_irq_handler()
1561 		gmbus_irq_handler(dev_priv);  in i965_pipestat_irq_handler()
1564 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,  in valleyview_pipestat_irq_handler()  argument
1569 	for_each_pipe(dev_priv, pipe) {  in valleyview_pipestat_irq_handler()
1571 			intel_handle_vblank(dev_priv, pipe);  in valleyview_pipestat_irq_handler()
1574 			flip_done_handler(dev_priv, pipe);  in valleyview_pipestat_irq_handler()
1577 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);  in valleyview_pipestat_irq_handler()
1580 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in valleyview_pipestat_irq_handler()
1584 		gmbus_irq_handler(dev_priv);  in valleyview_pipestat_irq_handler()
1587 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)  in i9xx_hpd_irq_ack()  argument
1592 	if (IS_G4X(dev_priv) ||  in i9xx_hpd_irq_ack()
1593 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in i9xx_hpd_irq_ack()
1609 		u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask;  in i9xx_hpd_irq_ack()
1615 		intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status);  in i9xx_hpd_irq_ack()
1618 	drm_WARN_ONCE(&dev_priv->drm, 1,  in i9xx_hpd_irq_ack()
1620 		      intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));  in i9xx_hpd_irq_ack()
1625 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,  in i9xx_hpd_irq_handler()  argument
1631 	if (IS_G4X(dev_priv) ||  in i9xx_hpd_irq_handler()
1632 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in i9xx_hpd_irq_handler()
1638 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in i9xx_hpd_irq_handler()
1640 				   dev_priv->display.hotplug.hpd,  in i9xx_hpd_irq_handler()
1643 		intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in i9xx_hpd_irq_handler()
1646 	if ((IS_G4X(dev_priv) ||  in i9xx_hpd_irq_handler()
1647 	     IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in i9xx_hpd_irq_handler()
1649 		dp_aux_irq_handler(dev_priv);  in i9xx_hpd_irq_handler()
1654 	struct drm_i915_private *dev_priv = arg;  in valleyview_irq_handler()  local
1657 	if (!intel_irqs_enabled(dev_priv))  in valleyview_irq_handler()
1661 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in valleyview_irq_handler()
1669 		gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);  in valleyview_irq_handler()
1670 		pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);  in valleyview_irq_handler()
1671 		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);  in valleyview_irq_handler()
1691 		intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);  in valleyview_irq_handler()
1692 		ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);  in valleyview_irq_handler()
1693 		intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);  in valleyview_irq_handler()
1696 			intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir);  in valleyview_irq_handler()
1698 			intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);  in valleyview_irq_handler()
1701 			hotplug_status = i9xx_hpd_irq_ack(dev_priv);  in valleyview_irq_handler()
1705 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in valleyview_irq_handler()
1709 			intel_lpe_audio_irq_handler(dev_priv);  in valleyview_irq_handler()
1716 			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);  in valleyview_irq_handler()
1718 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);  in valleyview_irq_handler()
1719 		intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);  in valleyview_irq_handler()
1722 			gen6_gt_irq_handler(to_gt(dev_priv), gt_iir);  in valleyview_irq_handler()
1724 			gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);  in valleyview_irq_handler()
1727 			i9xx_hpd_irq_handler(dev_priv, hotplug_status);  in valleyview_irq_handler()
1729 		valleyview_pipestat_irq_handler(dev_priv, pipe_stats);  in valleyview_irq_handler()
1732 	pmu_irq_stats(dev_priv, ret);  in valleyview_irq_handler()
1734 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in valleyview_irq_handler()
1741 	struct drm_i915_private *dev_priv = arg;  in cherryview_irq_handler()  local
1744 	if (!intel_irqs_enabled(dev_priv))  in cherryview_irq_handler()
1748 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in cherryview_irq_handler()
1756 		master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;  in cherryview_irq_handler()
1757 		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);  in cherryview_irq_handler()
1777 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);  in cherryview_irq_handler()
1778 		ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);  in cherryview_irq_handler()
1779 		intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);  in cherryview_irq_handler()
1781 		gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);  in cherryview_irq_handler()
1784 			hotplug_status = i9xx_hpd_irq_ack(dev_priv);  in cherryview_irq_handler()
1788 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in cherryview_irq_handler()
1793 			intel_lpe_audio_irq_handler(dev_priv);  in cherryview_irq_handler()
1800 			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);  in cherryview_irq_handler()
1802 		intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);  in cherryview_irq_handler()
1803 		intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);  in cherryview_irq_handler()
1806 			i9xx_hpd_irq_handler(dev_priv, hotplug_status);  in cherryview_irq_handler()
1808 		valleyview_pipestat_irq_handler(dev_priv, pipe_stats);  in cherryview_irq_handler()
1811 	pmu_irq_stats(dev_priv, ret);  in cherryview_irq_handler()
1813 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in cherryview_irq_handler()
1818 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,  in ibx_hpd_irq_handler()  argument
1829 	dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in ibx_hpd_irq_handler()
1838 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);  in ibx_hpd_irq_handler()
1842 	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in ibx_hpd_irq_handler()
1844 			   dev_priv->display.hotplug.pch_hpd,  in ibx_hpd_irq_handler()
1847 	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in ibx_hpd_irq_handler()
1850 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)  in ibx_irq_handler()  argument
1855 	ibx_hpd_irq_handler(dev_priv, hotplug_trigger);  in ibx_irq_handler()
1860 		drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",  in ibx_irq_handler()
1865 		dp_aux_irq_handler(dev_priv);  in ibx_irq_handler()
1868 		gmbus_irq_handler(dev_priv);  in ibx_irq_handler()
1871 		drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");  in ibx_irq_handler()
1874 		drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");  in ibx_irq_handler()
1877 		drm_err(&dev_priv->drm, "PCH poison interrupt\n");  in ibx_irq_handler()
1880 		for_each_pipe(dev_priv, pipe)  in ibx_irq_handler()
1881 			drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",  in ibx_irq_handler()
1883 				intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));  in ibx_irq_handler()
1887 		drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");  in ibx_irq_handler()
1890 		drm_dbg(&dev_priv->drm,  in ibx_irq_handler()
1894 		intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);  in ibx_irq_handler()
1897 		intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);  in ibx_irq_handler()
1900 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)  in ivb_err_int_handler()  argument
1902 	u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT);  in ivb_err_int_handler()
1906 		drm_err(&dev_priv->drm, "Poison interrupt\n");  in ivb_err_int_handler()
1908 	for_each_pipe(dev_priv, pipe) {  in ivb_err_int_handler()
1910 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in ivb_err_int_handler()
1913 			if (IS_IVYBRIDGE(dev_priv))  in ivb_err_int_handler()
1914 				ivb_pipe_crc_irq_handler(dev_priv, pipe);  in ivb_err_int_handler()
1916 				hsw_pipe_crc_irq_handler(dev_priv, pipe);  in ivb_err_int_handler()
1920 	intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int);  in ivb_err_int_handler()
1923 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)  in cpt_serr_int_handler()  argument
1925 	u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT);  in cpt_serr_int_handler()
1929 		drm_err(&dev_priv->drm, "PCH poison interrupt\n");  in cpt_serr_int_handler()
1931 	for_each_pipe(dev_priv, pipe)  in cpt_serr_int_handler()
1933 			intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);  in cpt_serr_int_handler()
1935 	intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int);  in cpt_serr_int_handler()
1938 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)  in cpt_irq_handler()  argument
1943 	ibx_hpd_irq_handler(dev_priv, hotplug_trigger);  in cpt_irq_handler()
1948 		drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",  in cpt_irq_handler()
1953 		dp_aux_irq_handler(dev_priv);  in cpt_irq_handler()
1956 		gmbus_irq_handler(dev_priv);  in cpt_irq_handler()
1959 		drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");  in cpt_irq_handler()
1962 		drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");  in cpt_irq_handler()
1965 		for_each_pipe(dev_priv, pipe)  in cpt_irq_handler()
1966 			drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",  in cpt_irq_handler()
1968 				intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));  in cpt_irq_handler()
1972 		cpt_serr_int_handler(dev_priv);  in cpt_irq_handler()
1975 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)  in icp_irq_handler()  argument
1984 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);  in icp_irq_handler()
1985 		intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg);  in icp_irq_handler()
1987 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in icp_irq_handler()
1989 				   dev_priv->display.hotplug.pch_hpd,  in icp_irq_handler()
1996 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);  in icp_irq_handler()
1997 		intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg);  in icp_irq_handler()
1999 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in icp_irq_handler()
2001 				   dev_priv->display.hotplug.pch_hpd,  in icp_irq_handler()
2006 		intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in icp_irq_handler()
2009 		gmbus_irq_handler(dev_priv);  in icp_irq_handler()
2012 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)  in spt_irq_handler()  argument
2022 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in spt_irq_handler()
2023 		intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);  in spt_irq_handler()
2025 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in spt_irq_handler()
2027 				   dev_priv->display.hotplug.pch_hpd,  in spt_irq_handler()
2034 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);  in spt_irq_handler()
2035 		intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg);  in spt_irq_handler()
2037 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in spt_irq_handler()
2039 				   dev_priv->display.hotplug.pch_hpd,  in spt_irq_handler()
2044 		intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in spt_irq_handler()
2047 		gmbus_irq_handler(dev_priv);  in spt_irq_handler()
2050 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,  in ilk_hpd_irq_handler()  argument
2055 	dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);  in ilk_hpd_irq_handler()
2056 	intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);  in ilk_hpd_irq_handler()
2058 	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in ilk_hpd_irq_handler()
2060 			   dev_priv->display.hotplug.hpd,  in ilk_hpd_irq_handler()
2063 	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in ilk_hpd_irq_handler()
2066 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,  in ilk_display_irq_handler()  argument
2073 		ilk_hpd_irq_handler(dev_priv, hotplug_trigger);  in ilk_display_irq_handler()
2076 		dp_aux_irq_handler(dev_priv);  in ilk_display_irq_handler()
2079 		intel_opregion_asle_intr(dev_priv);  in ilk_display_irq_handler()
2082 		drm_err(&dev_priv->drm, "Poison interrupt\n");  in ilk_display_irq_handler()
2084 	for_each_pipe(dev_priv, pipe) {  in ilk_display_irq_handler()
2086 			intel_handle_vblank(dev_priv, pipe);  in ilk_display_irq_handler()
2089 			flip_done_handler(dev_priv, pipe);  in ilk_display_irq_handler()
2092 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in ilk_display_irq_handler()
2095 			i9xx_pipe_crc_irq_handler(dev_priv, pipe);  in ilk_display_irq_handler()
2100 		u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);  in ilk_display_irq_handler()
2102 		if (HAS_PCH_CPT(dev_priv))  in ilk_display_irq_handler()
2103 			cpt_irq_handler(dev_priv, pch_iir);  in ilk_display_irq_handler()
2105 			ibx_irq_handler(dev_priv, pch_iir);  in ilk_display_irq_handler()
2108 		intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);  in ilk_display_irq_handler()
2111 	if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)  in ilk_display_irq_handler()
2112 		gen5_rps_irq_handler(&to_gt(dev_priv)->rps);  in ilk_display_irq_handler()
2115 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,  in ivb_display_irq_handler()  argument
2122 		ilk_hpd_irq_handler(dev_priv, hotplug_trigger);  in ivb_display_irq_handler()
2125 		ivb_err_int_handler(dev_priv);  in ivb_display_irq_handler()
2128 		dp_aux_irq_handler(dev_priv);  in ivb_display_irq_handler()
2131 		intel_opregion_asle_intr(dev_priv);  in ivb_display_irq_handler()
2133 	for_each_pipe(dev_priv, pipe) {  in ivb_display_irq_handler()
2135 			intel_handle_vblank(dev_priv, pipe);  in ivb_display_irq_handler()
2138 			flip_done_handler(dev_priv, pipe);  in ivb_display_irq_handler()
2142 	if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {  in ivb_display_irq_handler()
2143 		u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);  in ivb_display_irq_handler()
2145 		cpt_irq_handler(dev_priv, pch_iir);  in ivb_display_irq_handler()
2148 		intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);  in ivb_display_irq_handler()
2230 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,  in bxt_hpd_irq_handler()  argument
2235 	dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in bxt_hpd_irq_handler()
2236 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);  in bxt_hpd_irq_handler()
2238 	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in bxt_hpd_irq_handler()
2240 			   dev_priv->display.hotplug.hpd,  in bxt_hpd_irq_handler()
2243 	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in bxt_hpd_irq_handler()
2246 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)  in gen11_hpd_irq_handler()  argument
2255 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);  in gen11_hpd_irq_handler()
2256 		intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);  in gen11_hpd_irq_handler()
2258 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in gen11_hpd_irq_handler()
2260 				   dev_priv->display.hotplug.hpd,  in gen11_hpd_irq_handler()
2267 		dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);  in gen11_hpd_irq_handler()
2268 		intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);  in gen11_hpd_irq_handler()
2270 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,  in gen11_hpd_irq_handler()
2272 				   dev_priv->display.hotplug.hpd,  in gen11_hpd_irq_handler()
2277 		intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);  in gen11_hpd_irq_handler()
2279 		drm_err(&dev_priv->drm,  in gen11_hpd_irq_handler()
2283 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)  in gen8_de_port_aux_mask()  argument
2287 	if (DISPLAY_VER(dev_priv) >= 13)  in gen8_de_port_aux_mask()
2297 	else if (DISPLAY_VER(dev_priv) >= 12)  in gen8_de_port_aux_mask()
2310 	if (DISPLAY_VER(dev_priv) >= 9)  in gen8_de_port_aux_mask()
2315 	if (DISPLAY_VER(dev_priv) == 11) {  in gen8_de_port_aux_mask()
2323 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)  in gen8_de_pipe_fault_mask()  argument
2325 	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))  in gen8_de_pipe_fault_mask()
2327 	else if (DISPLAY_VER(dev_priv) >= 11)  in gen8_de_pipe_fault_mask()
2329 	else if (DISPLAY_VER(dev_priv) >= 9)  in gen8_de_pipe_fault_mask()
2336 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)  in gen8_de_misc_irq_handler()  argument
2341 		intel_opregion_asle_intr(dev_priv);  in gen8_de_misc_irq_handler()
2350 		for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {  in gen8_de_misc_irq_handler()
2353 			if (DISPLAY_VER(dev_priv) >= 12)  in gen8_de_misc_irq_handler()
2358 			psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg);  in gen8_de_misc_irq_handler()
2359 			intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir);  in gen8_de_misc_irq_handler()
2367 			if (DISPLAY_VER(dev_priv) < 12)  in gen8_de_misc_irq_handler()
2373 		drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");  in gen8_de_misc_irq_handler()
2376 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,  in gen11_dsi_te_interrupt_handler()  argument
2388 	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));  in gen11_dsi_te_interrupt_handler()
2400 	val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans));  in gen11_dsi_te_interrupt_handler()
2404 		drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");  in gen11_dsi_te_interrupt_handler()
2409 	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans));  in gen11_dsi_te_interrupt_handler()
2421 		drm_err(&dev_priv->drm, "Invalid PIPE\n");  in gen11_dsi_te_interrupt_handler()
2425 	intel_handle_vblank(dev_priv, pipe);  in gen11_dsi_te_interrupt_handler()
2429 	tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));  in gen11_dsi_te_interrupt_handler()
2430 	intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);  in gen11_dsi_te_interrupt_handler()
2441 u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv)  in gen8_de_pipe_underrun_mask()  argument
2445 	if (DISPLAY_VER(dev_priv) >= 13)  in gen8_de_pipe_underrun_mask()
2453 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)  in gen8_de_irq_handler()  argument
2459 	drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv));  in gen8_de_irq_handler()
2462 		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);  in gen8_de_irq_handler()
2464 			intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir);  in gen8_de_irq_handler()
2466 			gen8_de_misc_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
2468 			drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2473 	if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {  in gen8_de_irq_handler()
2474 		iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);  in gen8_de_irq_handler()
2476 			intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);  in gen8_de_irq_handler()
2478 			gen11_hpd_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
2480 			drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2486 		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR);  in gen8_de_irq_handler()
2490 			intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir);  in gen8_de_irq_handler()
2493 			if (iir & gen8_de_port_aux_mask(dev_priv)) {  in gen8_de_irq_handler()
2494 				dp_aux_irq_handler(dev_priv);  in gen8_de_irq_handler()
2498 			if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {  in gen8_de_irq_handler()
2502 					bxt_hpd_irq_handler(dev_priv, hotplug_trigger);  in gen8_de_irq_handler()
2505 			} else if (IS_BROADWELL(dev_priv)) {  in gen8_de_irq_handler()
2509 					ilk_hpd_irq_handler(dev_priv, hotplug_trigger);  in gen8_de_irq_handler()
2514 			if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&  in gen8_de_irq_handler()
2516 				gmbus_irq_handler(dev_priv);  in gen8_de_irq_handler()
2520 			if (DISPLAY_VER(dev_priv) >= 11) {  in gen8_de_irq_handler()
2524 					gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);  in gen8_de_irq_handler()
2530 				drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2534 			drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2538 	for_each_pipe(dev_priv, pipe) {  in gen8_de_irq_handler()
2544 		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe));  in gen8_de_irq_handler()
2546 			drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2552 		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir);  in gen8_de_irq_handler()
2555 			intel_handle_vblank(dev_priv, pipe);  in gen8_de_irq_handler()
2557 		if (iir & gen8_de_pipe_flip_done_mask(dev_priv))  in gen8_de_irq_handler()
2558 			flip_done_handler(dev_priv, pipe);  in gen8_de_irq_handler()
2561 			hsw_pipe_crc_irq_handler(dev_priv, pipe);  in gen8_de_irq_handler()
2563 		if (iir & gen8_de_pipe_underrun_mask(dev_priv))  in gen8_de_irq_handler()
2564 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);  in gen8_de_irq_handler()
2566 		fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);  in gen8_de_irq_handler()
2568 			drm_err(&dev_priv->drm,  in gen8_de_irq_handler()
2574 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&  in gen8_de_irq_handler()
2581 		iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);  in gen8_de_irq_handler()
2583 			intel_uncore_write(&dev_priv->uncore, SDEIIR, iir);  in gen8_de_irq_handler()
2586 			if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in gen8_de_irq_handler()
2587 				icp_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
2588 			else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)  in gen8_de_irq_handler()
2589 				spt_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
2591 				cpt_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
2597 			drm_dbg(&dev_priv->drm,  in gen8_de_irq_handler()
2625 	struct drm_i915_private *dev_priv = arg;  in gen8_irq_handler()  local
2626 	void __iomem * const regs = dev_priv->uncore.regs;  in gen8_irq_handler()
2629 	if (!intel_irqs_enabled(dev_priv))  in gen8_irq_handler()
2639 	gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);  in gen8_irq_handler()
2643 		disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in gen8_irq_handler()
2644 		gen8_de_irq_handler(dev_priv, master_ctl);  in gen8_irq_handler()
2645 		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in gen8_irq_handler()
2650 	pmu_irq_stats(dev_priv, IRQ_HANDLED);  in gen8_irq_handler()
2820 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i8xx_enable_vblank()  local
2824 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in i8xx_enable_vblank()
2825 	i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);  in i8xx_enable_vblank()
2826 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in i8xx_enable_vblank()
2833 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i915gm_enable_vblank()  local
2841 	if (dev_priv->vblank_enabled++ == 0)  in i915gm_enable_vblank()
2842 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));  in i915gm_enable_vblank()
2849 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i965_enable_vblank()  local
2853 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in i965_enable_vblank()
2854 	i915_enable_pipestat(dev_priv, pipe,  in i965_enable_vblank()
2856 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in i965_enable_vblank()
2863 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in ilk_enable_vblank()  local
2866 	u32 bit = DISPLAY_VER(dev_priv) >= 7 ?  in ilk_enable_vblank()
2869 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in ilk_enable_vblank()
2870 	ilk_enable_display_irq(dev_priv, bit);  in ilk_enable_vblank()
2871 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in ilk_enable_vblank()
2876 	if (HAS_PSR(dev_priv))  in ilk_enable_vblank()
2885 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);  in gen11_dsi_configure_te()  local
2899 	tmp =  intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port));  in gen11_dsi_configure_te()
2905 	intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp);  in gen11_dsi_configure_te()
2907 	tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));  in gen11_dsi_configure_te()
2908 	intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);  in gen11_dsi_configure_te()
2916 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_enable_vblank()  local
2923 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in bdw_enable_vblank()
2924 	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);  in bdw_enable_vblank()
2925 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in bdw_enable_vblank()
2930 	if (HAS_PSR(dev_priv))  in bdw_enable_vblank()
2941 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i8xx_disable_vblank()  local
2945 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in i8xx_disable_vblank()
2946 	i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);  in i8xx_disable_vblank()
2947 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in i8xx_disable_vblank()
2952 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i915gm_disable_vblank()  local
2956 	if (--dev_priv->vblank_enabled == 0)  in i915gm_disable_vblank()
2957 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)…  in i915gm_disable_vblank()
2962 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in i965_disable_vblank()  local
2966 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in i965_disable_vblank()
2967 	i915_disable_pipestat(dev_priv, pipe,  in i965_disable_vblank()
2969 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in i965_disable_vblank()
2974 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);  in ilk_disable_vblank()  local
2977 	u32 bit = DISPLAY_VER(dev_priv) >= 7 ?  in ilk_disable_vblank()
2980 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in ilk_disable_vblank()
2981 	ilk_disable_display_irq(dev_priv, bit);  in ilk_disable_vblank()
2982 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in ilk_disable_vblank()
2988 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_disable_vblank()  local
2995 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);  in bdw_disable_vblank()
2996 	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);  in bdw_disable_vblank()
2997 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);  in bdw_disable_vblank()
3000 static void ibx_irq_reset(struct drm_i915_private *dev_priv)  in ibx_irq_reset()  argument
3002 	struct intel_uncore *uncore = &dev_priv->uncore;  in ibx_irq_reset()
3004 	if (HAS_PCH_NOP(dev_priv))  in ibx_irq_reset()
3009 	if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))  in ibx_irq_reset()
3010 		intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);  in ibx_irq_reset()
3013 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)  in vlv_display_irq_reset()  argument
3015 	struct intel_uncore *uncore = &dev_priv->uncore;  in vlv_display_irq_reset()
3017 	if (IS_CHERRYVIEW(dev_priv))  in vlv_display_irq_reset()
3022 	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);  in vlv_display_irq_reset()
3023 …intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_ST…  in vlv_display_irq_reset()
3025 	i9xx_pipestat_irq_reset(dev_priv);  in vlv_display_irq_reset()
3028 	dev_priv->irq_mask = ~0u;  in vlv_display_irq_reset()
3031 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)  in vlv_display_irq_postinstall()  argument
3033 	struct intel_uncore *uncore = &dev_priv->uncore;  in vlv_display_irq_postinstall()
3041 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);  in vlv_display_irq_postinstall()
3042 	for_each_pipe(dev_priv, pipe)  in vlv_display_irq_postinstall()
3043 		i915_enable_pipestat(dev_priv, pipe, pipestat_mask);  in vlv_display_irq_postinstall()
3051 	if (IS_CHERRYVIEW(dev_priv))  in vlv_display_irq_postinstall()
3055 	drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);  in vlv_display_irq_postinstall()
3057 	dev_priv->irq_mask = ~enable_mask;  in vlv_display_irq_postinstall()
3059 	GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);  in vlv_display_irq_postinstall()
3064 static void ilk_irq_reset(struct drm_i915_private *dev_priv)  in ilk_irq_reset()  argument
3066 	struct intel_uncore *uncore = &dev_priv->uncore;  in ilk_irq_reset()
3069 	dev_priv->irq_mask = ~0u;  in ilk_irq_reset()
3071 	if (GRAPHICS_VER(dev_priv) == 7)  in ilk_irq_reset()
3074 	if (IS_HASWELL(dev_priv)) {  in ilk_irq_reset()
3079 	gen5_gt_irq_reset(to_gt(dev_priv));  in ilk_irq_reset()
3081 	ibx_irq_reset(dev_priv);  in ilk_irq_reset()
3084 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)  in valleyview_irq_reset()  argument
3086 	intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);  in valleyview_irq_reset()
3087 	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);  in valleyview_irq_reset()
3089 	gen5_gt_irq_reset(to_gt(dev_priv));  in valleyview_irq_reset()
3091 	spin_lock_irq(&dev_priv->irq_lock);  in valleyview_irq_reset()
3092 	if (dev_priv->display_irqs_enabled)  in valleyview_irq_reset()
3093 		vlv_display_irq_reset(dev_priv);  in valleyview_irq_reset()
3094 	spin_unlock_irq(&dev_priv->irq_lock);  in valleyview_irq_reset()
3097 static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)  in gen8_display_irq_reset()  argument
3099 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_display_irq_reset()
3102 	if (!HAS_DISPLAY(dev_priv))  in gen8_display_irq_reset()
3108 	for_each_pipe(dev_priv, pipe)  in gen8_display_irq_reset()
3109 		if (intel_display_power_is_enabled(dev_priv,  in gen8_display_irq_reset()
3117 static void gen8_irq_reset(struct drm_i915_private *dev_priv)  in gen8_irq_reset()  argument
3119 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_irq_reset()
3121 	gen8_master_intr_disable(dev_priv->uncore.regs);  in gen8_irq_reset()
3123 	gen8_gt_irq_reset(to_gt(dev_priv));  in gen8_irq_reset()
3124 	gen8_display_irq_reset(dev_priv);  in gen8_irq_reset()
3127 	if (HAS_PCH_SPLIT(dev_priv))  in gen8_irq_reset()
3128 		ibx_irq_reset(dev_priv);  in gen8_irq_reset()
3132 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)  in gen11_display_irq_reset()  argument
3134 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen11_display_irq_reset()
3139 	if (!HAS_DISPLAY(dev_priv))  in gen11_display_irq_reset()
3144 	if (DISPLAY_VER(dev_priv) >= 12) {  in gen11_display_irq_reset()
3147 		for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {  in gen11_display_irq_reset()
3151 			if (!intel_display_power_is_enabled(dev_priv, domain))  in gen11_display_irq_reset()
3162 	for_each_pipe(dev_priv, pipe)  in gen11_display_irq_reset()
3163 		if (intel_display_power_is_enabled(dev_priv,  in gen11_display_irq_reset()
3171 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in gen11_display_irq_reset()
3175 static void gen11_irq_reset(struct drm_i915_private *dev_priv)  in gen11_irq_reset()  argument
3177 	struct intel_gt *gt = to_gt(dev_priv);  in gen11_irq_reset()
3180 	gen11_master_intr_disable(dev_priv->uncore.regs);  in gen11_irq_reset()
3183 	gen11_display_irq_reset(dev_priv);  in gen11_irq_reset()
3189 static void dg1_irq_reset(struct drm_i915_private *dev_priv)  in dg1_irq_reset()  argument
3191 	struct intel_gt *gt = to_gt(dev_priv);  in dg1_irq_reset()
3194 	dg1_master_intr_disable(dev_priv->uncore.regs);  in dg1_irq_reset()
3197 	gen11_display_irq_reset(dev_priv);  in dg1_irq_reset()
3203 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,  in gen8_irq_power_well_post_enable()  argument
3206 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_irq_power_well_post_enable()
3208 		gen8_de_pipe_underrun_mask(dev_priv) |  in gen8_irq_power_well_post_enable()
3209 		gen8_de_pipe_flip_done_mask(dev_priv);  in gen8_irq_power_well_post_enable()
3212 	spin_lock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_post_enable()
3214 	if (!intel_irqs_enabled(dev_priv)) {  in gen8_irq_power_well_post_enable()
3215 		spin_unlock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_post_enable()
3219 	for_each_pipe_masked(dev_priv, pipe, pipe_mask)  in gen8_irq_power_well_post_enable()
3221 				  dev_priv->de_irq_mask[pipe],  in gen8_irq_power_well_post_enable()
3222 				  ~dev_priv->de_irq_mask[pipe] | extra_ier);  in gen8_irq_power_well_post_enable()
3224 	spin_unlock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_post_enable()
3227 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,  in gen8_irq_power_well_pre_disable()  argument
3230 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_irq_power_well_pre_disable()
3233 	spin_lock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_pre_disable()
3235 	if (!intel_irqs_enabled(dev_priv)) {  in gen8_irq_power_well_pre_disable()
3236 		spin_unlock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_pre_disable()
3240 	for_each_pipe_masked(dev_priv, pipe, pipe_mask)  in gen8_irq_power_well_pre_disable()
3243 	spin_unlock_irq(&dev_priv->irq_lock);  in gen8_irq_power_well_pre_disable()
3246 	intel_synchronize_irq(dev_priv);  in gen8_irq_power_well_pre_disable()
3249 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)  in cherryview_irq_reset()  argument
3251 	struct intel_uncore *uncore = &dev_priv->uncore;  in cherryview_irq_reset()
3253 	intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);  in cherryview_irq_reset()
3254 	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);  in cherryview_irq_reset()
3256 	gen8_gt_irq_reset(to_gt(dev_priv));  in cherryview_irq_reset()
3260 	spin_lock_irq(&dev_priv->irq_lock);  in cherryview_irq_reset()
3261 	if (dev_priv->display_irqs_enabled)  in cherryview_irq_reset()
3262 		vlv_display_irq_reset(dev_priv);  in cherryview_irq_reset()
3263 	spin_unlock_irq(&dev_priv->irq_lock);  in cherryview_irq_reset()
3291 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)  in ibx_hpd_detection_setup()  argument
3300 	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in ibx_hpd_detection_setup()
3308 	hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);  in ibx_hpd_detection_setup()
3309 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);  in ibx_hpd_detection_setup()
3312 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)  in ibx_hpd_irq_setup()  argument
3316 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);  in ibx_hpd_irq_setup()
3317 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);  in ibx_hpd_irq_setup()
3319 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);  in ibx_hpd_irq_setup()
3321 	ibx_hpd_detection_setup(dev_priv);  in ibx_hpd_irq_setup()
3354 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)  in icp_ddi_hpd_detection_setup()  argument
3358 	hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);  in icp_ddi_hpd_detection_setup()
3363 	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);  in icp_ddi_hpd_detection_setup()
3364 	intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug);  in icp_ddi_hpd_detection_setup()
3367 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)  in icp_tc_hpd_detection_setup()  argument
3371 	hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);  in icp_tc_hpd_detection_setup()
3378 	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);  in icp_tc_hpd_detection_setup()
3379 	intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug);  in icp_tc_hpd_detection_setup()
3382 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)  in icp_hpd_irq_setup()  argument
3386 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);  in icp_hpd_irq_setup()
3387 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);  in icp_hpd_irq_setup()
3389 	if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)  in icp_hpd_irq_setup()
3390 		intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);  in icp_hpd_irq_setup()
3392 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);  in icp_hpd_irq_setup()
3394 	icp_ddi_hpd_detection_setup(dev_priv);  in icp_hpd_irq_setup()
3395 	icp_tc_hpd_detection_setup(dev_priv);  in icp_hpd_irq_setup()
3414 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)  in dg1_hpd_irq_setup()  argument
3418 	val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);  in dg1_hpd_irq_setup()
3423 	intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);  in dg1_hpd_irq_setup()
3425 	icp_hpd_irq_setup(dev_priv);  in dg1_hpd_irq_setup()
3428 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)  in gen11_tc_hpd_detection_setup()  argument
3432 	hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);  in gen11_tc_hpd_detection_setup()
3439 	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);  in gen11_tc_hpd_detection_setup()
3440 	intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug);  in gen11_tc_hpd_detection_setup()
3443 static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)  in gen11_tbt_hpd_detection_setup()  argument
3447 	hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);  in gen11_tbt_hpd_detection_setup()
3454 	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);  in gen11_tbt_hpd_detection_setup()
3455 	intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug);  in gen11_tbt_hpd_detection_setup()
3458 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)  in gen11_hpd_irq_setup()  argument
3463 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);  in gen11_hpd_irq_setup()
3464 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);  in gen11_hpd_irq_setup()
3466 	val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);  in gen11_hpd_irq_setup()
3469 	intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val);  in gen11_hpd_irq_setup()
3470 	intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);  in gen11_hpd_irq_setup()
3472 	gen11_tc_hpd_detection_setup(dev_priv);  in gen11_hpd_irq_setup()
3473 	gen11_tbt_hpd_detection_setup(dev_priv);  in gen11_hpd_irq_setup()
3475 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in gen11_hpd_irq_setup()
3476 		icp_hpd_irq_setup(dev_priv);  in gen11_hpd_irq_setup()
3507 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)  in spt_hpd_detection_setup()  argument
3512 	if (HAS_PCH_CNP(dev_priv)) {  in spt_hpd_detection_setup()
3513 		val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);  in spt_hpd_detection_setup()
3516 		intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);  in spt_hpd_detection_setup()
3520 	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in spt_hpd_detection_setup()
3525 	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);  in spt_hpd_detection_setup()
3526 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);  in spt_hpd_detection_setup()
3528 	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);  in spt_hpd_detection_setup()
3530 	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);  in spt_hpd_detection_setup()
3531 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug);  in spt_hpd_detection_setup()
3534 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)  in spt_hpd_irq_setup()  argument
3538 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)  in spt_hpd_irq_setup()
3539 		intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);  in spt_hpd_irq_setup()
3541 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);  in spt_hpd_irq_setup()
3542 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);  in spt_hpd_irq_setup()
3544 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);  in spt_hpd_irq_setup()
3546 	spt_hpd_detection_setup(dev_priv);  in spt_hpd_irq_setup()
3561 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)  in ilk_hpd_detection_setup()  argument
3570 	hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);  in ilk_hpd_detection_setup()
3573 	hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);  in ilk_hpd_detection_setup()
3574 	intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);  in ilk_hpd_detection_setup()
3577 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)  in ilk_hpd_irq_setup()  argument
3581 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);  in ilk_hpd_irq_setup()
3582 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);  in ilk_hpd_irq_setup()
3584 	if (DISPLAY_VER(dev_priv) >= 8)  in ilk_hpd_irq_setup()
3585 		bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);  in ilk_hpd_irq_setup()
3587 		ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);  in ilk_hpd_irq_setup()
3589 	ilk_hpd_detection_setup(dev_priv);  in ilk_hpd_irq_setup()
3591 	ibx_hpd_irq_setup(dev_priv);  in ilk_hpd_irq_setup()
3620 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)  in bxt_hpd_detection_setup()  argument
3624 	hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);  in bxt_hpd_detection_setup()
3631 	hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);  in bxt_hpd_detection_setup()
3632 	intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);  in bxt_hpd_detection_setup()
3635 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)  in bxt_hpd_irq_setup()  argument
3639 	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);  in bxt_hpd_irq_setup()
3640 	hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);  in bxt_hpd_irq_setup()
3642 	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);  in bxt_hpd_irq_setup()
3644 	bxt_hpd_detection_setup(dev_priv);  in bxt_hpd_irq_setup()
3658 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)  in ibx_irq_postinstall()  argument
3660 	struct intel_uncore *uncore = &dev_priv->uncore;  in ibx_irq_postinstall()
3663 	if (HAS_PCH_NOP(dev_priv))  in ibx_irq_postinstall()
3666 	if (HAS_PCH_IBX(dev_priv))  in ibx_irq_postinstall()
3668 	else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))  in ibx_irq_postinstall()
3676 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)  in ilk_irq_postinstall()  argument
3678 	struct intel_uncore *uncore = &dev_priv->uncore;  in ilk_irq_postinstall()
3681 	if (GRAPHICS_VER(dev_priv) >= 7) {  in ilk_irq_postinstall()
3701 	if (IS_HASWELL(dev_priv)) {  in ilk_irq_postinstall()
3706 	if (IS_IRONLAKE_M(dev_priv))  in ilk_irq_postinstall()
3709 	dev_priv->irq_mask = ~display_mask;  in ilk_irq_postinstall()
3711 	ibx_irq_postinstall(dev_priv);  in ilk_irq_postinstall()
3713 	gen5_gt_irq_postinstall(to_gt(dev_priv));  in ilk_irq_postinstall()
3715 	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,  in ilk_irq_postinstall()
3719 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)  in valleyview_enable_display_irqs()  argument
3721 	lockdep_assert_held(&dev_priv->irq_lock);  in valleyview_enable_display_irqs()
3723 	if (dev_priv->display_irqs_enabled)  in valleyview_enable_display_irqs()
3726 	dev_priv->display_irqs_enabled = true;  in valleyview_enable_display_irqs()
3728 	if (intel_irqs_enabled(dev_priv)) {  in valleyview_enable_display_irqs()
3729 		vlv_display_irq_reset(dev_priv);  in valleyview_enable_display_irqs()
3730 		vlv_display_irq_postinstall(dev_priv);  in valleyview_enable_display_irqs()
3734 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)  in valleyview_disable_display_irqs()  argument
3736 	lockdep_assert_held(&dev_priv->irq_lock);  in valleyview_disable_display_irqs()
3738 	if (!dev_priv->display_irqs_enabled)  in valleyview_disable_display_irqs()
3741 	dev_priv->display_irqs_enabled = false;  in valleyview_disable_display_irqs()
3743 	if (intel_irqs_enabled(dev_priv))  in valleyview_disable_display_irqs()
3744 		vlv_display_irq_reset(dev_priv);  in valleyview_disable_display_irqs()
3748 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)  in valleyview_irq_postinstall()  argument
3750 	gen5_gt_irq_postinstall(to_gt(dev_priv));  in valleyview_irq_postinstall()
3752 	spin_lock_irq(&dev_priv->irq_lock);  in valleyview_irq_postinstall()
3753 	if (dev_priv->display_irqs_enabled)  in valleyview_irq_postinstall()
3754 		vlv_display_irq_postinstall(dev_priv);  in valleyview_irq_postinstall()
3755 	spin_unlock_irq(&dev_priv->irq_lock);  in valleyview_irq_postinstall()
3757 	intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);  in valleyview_irq_postinstall()
3758 	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);  in valleyview_irq_postinstall()
3761 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)  in gen8_de_irq_postinstall()  argument
3763 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_de_irq_postinstall()
3765 	u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |  in gen8_de_irq_postinstall()
3768 	u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);  in gen8_de_irq_postinstall()
3775 	if (!HAS_DISPLAY(dev_priv))  in gen8_de_irq_postinstall()
3778 	if (DISPLAY_VER(dev_priv) <= 10)  in gen8_de_irq_postinstall()
3781 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))  in gen8_de_irq_postinstall()
3784 	if (DISPLAY_VER(dev_priv) >= 11) {  in gen8_de_irq_postinstall()
3787 		if (intel_bios_is_dsi_present(dev_priv, &port))  in gen8_de_irq_postinstall()
3793 		gen8_de_pipe_underrun_mask(dev_priv) |  in gen8_de_irq_postinstall()
3794 		gen8_de_pipe_flip_done_mask(dev_priv);  in gen8_de_irq_postinstall()
3797 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))  in gen8_de_irq_postinstall()
3799 	else if (IS_BROADWELL(dev_priv))  in gen8_de_irq_postinstall()
3802 	if (DISPLAY_VER(dev_priv) >= 12) {  in gen8_de_irq_postinstall()
3805 		for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {  in gen8_de_irq_postinstall()
3809 			if (!intel_display_power_is_enabled(dev_priv, domain))  in gen8_de_irq_postinstall()
3818 	for_each_pipe(dev_priv, pipe) {  in gen8_de_irq_postinstall()
3819 		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;  in gen8_de_irq_postinstall()
3821 		if (intel_display_power_is_enabled(dev_priv,  in gen8_de_irq_postinstall()
3824 					  dev_priv->de_irq_mask[pipe],  in gen8_de_irq_postinstall()
3831 	if (DISPLAY_VER(dev_priv) >= 11) {  in gen8_de_irq_postinstall()
3841 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)  in icp_irq_postinstall()  argument
3843 	struct intel_uncore *uncore = &dev_priv->uncore;  in icp_irq_postinstall()
3849 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)  in gen8_irq_postinstall()  argument
3851 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in gen8_irq_postinstall()
3852 		icp_irq_postinstall(dev_priv);  in gen8_irq_postinstall()
3853 	else if (HAS_PCH_SPLIT(dev_priv))  in gen8_irq_postinstall()
3854 		ibx_irq_postinstall(dev_priv);  in gen8_irq_postinstall()
3856 	gen8_gt_irq_postinstall(to_gt(dev_priv));  in gen8_irq_postinstall()
3857 	gen8_de_irq_postinstall(dev_priv);  in gen8_irq_postinstall()
3859 	gen8_master_intr_enable(dev_priv->uncore.regs);  in gen8_irq_postinstall()
3862 static void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)  in gen11_de_irq_postinstall()  argument
3864 	if (!HAS_DISPLAY(dev_priv))  in gen11_de_irq_postinstall()
3867 	gen8_de_irq_postinstall(dev_priv);  in gen11_de_irq_postinstall()
3869 	intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,  in gen11_de_irq_postinstall()
3873 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)  in gen11_irq_postinstall()  argument
3875 	struct intel_gt *gt = to_gt(dev_priv);  in gen11_irq_postinstall()
3879 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in gen11_irq_postinstall()
3880 		icp_irq_postinstall(dev_priv);  in gen11_irq_postinstall()
3883 	gen11_de_irq_postinstall(dev_priv);  in gen11_irq_postinstall()
3888 	intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);  in gen11_irq_postinstall()
3891 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)  in dg1_irq_postinstall()  argument
3893 	struct intel_gt *gt = to_gt(dev_priv);  in dg1_irq_postinstall()
3901 	if (HAS_DISPLAY(dev_priv)) {  in dg1_irq_postinstall()
3902 		icp_irq_postinstall(dev_priv);  in dg1_irq_postinstall()
3903 		gen8_de_irq_postinstall(dev_priv);  in dg1_irq_postinstall()
3904 		intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,  in dg1_irq_postinstall()
3912 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)  in cherryview_irq_postinstall()  argument
3914 	gen8_gt_irq_postinstall(to_gt(dev_priv));  in cherryview_irq_postinstall()
3916 	spin_lock_irq(&dev_priv->irq_lock);  in cherryview_irq_postinstall()
3917 	if (dev_priv->display_irqs_enabled)  in cherryview_irq_postinstall()
3918 		vlv_display_irq_postinstall(dev_priv);  in cherryview_irq_postinstall()
3919 	spin_unlock_irq(&dev_priv->irq_lock);  in cherryview_irq_postinstall()
3921 	intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);  in cherryview_irq_postinstall()
3922 	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);  in cherryview_irq_postinstall()
3925 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)  in i8xx_irq_reset()  argument
3927 	struct intel_uncore *uncore = &dev_priv->uncore;  in i8xx_irq_reset()
3929 	i9xx_pipestat_irq_reset(dev_priv);  in i8xx_irq_reset()
3932 	dev_priv->irq_mask = ~0u;  in i8xx_irq_reset()
3935 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)  in i8xx_irq_postinstall()  argument
3937 	struct intel_uncore *uncore = &dev_priv->uncore;  in i8xx_irq_postinstall()
3946 	dev_priv->irq_mask =  in i8xx_irq_postinstall()
3957 	GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);  in i8xx_irq_postinstall()
3961 	spin_lock_irq(&dev_priv->irq_lock);  in i8xx_irq_postinstall()
3962 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i8xx_irq_postinstall()
3963 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i8xx_irq_postinstall()
3964 	spin_unlock_irq(&dev_priv->irq_lock);  in i8xx_irq_postinstall()
3997 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,  in i8xx_error_irq_handler()  argument
4003 		drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",  in i8xx_error_irq_handler()
4007 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,  in i9xx_error_irq_ack()  argument
4012 	*eir = intel_uncore_read(&dev_priv->uncore, EIR);  in i9xx_error_irq_ack()
4014 	intel_uncore_write(&dev_priv->uncore, EIR, *eir);  in i9xx_error_irq_ack()
4016 	*eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);  in i9xx_error_irq_ack()
4030 	emr = intel_uncore_read(&dev_priv->uncore, EMR);  in i9xx_error_irq_ack()
4031 	intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);  in i9xx_error_irq_ack()
4032 	intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);  in i9xx_error_irq_ack()
4035 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,  in i9xx_error_irq_handler()  argument
4041 		drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",  in i9xx_error_irq_handler()
4047 	struct drm_i915_private *dev_priv = arg;  in i8xx_irq_handler()  local
4050 	if (!intel_irqs_enabled(dev_priv))  in i8xx_irq_handler()
4054 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i8xx_irq_handler()
4061 		iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);  in i8xx_irq_handler()
4069 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in i8xx_irq_handler()
4072 			i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);  in i8xx_irq_handler()
4074 		intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);  in i8xx_irq_handler()
4077 			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);  in i8xx_irq_handler()
4080 			i8xx_error_irq_handler(dev_priv, eir, eir_stuck);  in i8xx_irq_handler()
4082 		i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);  in i8xx_irq_handler()
4085 	pmu_irq_stats(dev_priv, ret);  in i8xx_irq_handler()
4087 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i8xx_irq_handler()
4092 static void i915_irq_reset(struct drm_i915_private *dev_priv)  in i915_irq_reset()  argument
4094 	struct intel_uncore *uncore = &dev_priv->uncore;  in i915_irq_reset()
4096 	if (I915_HAS_HOTPLUG(dev_priv)) {  in i915_irq_reset()
4097 		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);  in i915_irq_reset()
4098 …intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT…  in i915_irq_reset()
4101 	i9xx_pipestat_irq_reset(dev_priv);  in i915_irq_reset()
4104 	dev_priv->irq_mask = ~0u;  in i915_irq_reset()
4107 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)  in i915_irq_postinstall()  argument
4109 	struct intel_uncore *uncore = &dev_priv->uncore;  in i915_irq_postinstall()
4112 	intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE |  in i915_irq_postinstall()
4116 	dev_priv->irq_mask =  in i915_irq_postinstall()
4129 	if (I915_HAS_HOTPLUG(dev_priv)) {  in i915_irq_postinstall()
4133 		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;  in i915_irq_postinstall()
4136 	GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);  in i915_irq_postinstall()
4140 	spin_lock_irq(&dev_priv->irq_lock);  in i915_irq_postinstall()
4141 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i915_irq_postinstall()
4142 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i915_irq_postinstall()
4143 	spin_unlock_irq(&dev_priv->irq_lock);  in i915_irq_postinstall()
4145 	i915_enable_asle_pipestat(dev_priv);  in i915_irq_postinstall()
4150 	struct drm_i915_private *dev_priv = arg;  in i915_irq_handler()  local
4153 	if (!intel_irqs_enabled(dev_priv))  in i915_irq_handler()
4157 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i915_irq_handler()
4165 		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);  in i915_irq_handler()
4171 		if (I915_HAS_HOTPLUG(dev_priv) &&  in i915_irq_handler()
4173 			hotplug_status = i9xx_hpd_irq_ack(dev_priv);  in i915_irq_handler()
4177 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in i915_irq_handler()
4180 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);  in i915_irq_handler()
4182 		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);  in i915_irq_handler()
4185 			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);  in i915_irq_handler()
4188 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);  in i915_irq_handler()
4191 			i9xx_hpd_irq_handler(dev_priv, hotplug_status);  in i915_irq_handler()
4193 		i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);  in i915_irq_handler()
4196 	pmu_irq_stats(dev_priv, ret);  in i915_irq_handler()
4198 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i915_irq_handler()
4203 static void i965_irq_reset(struct drm_i915_private *dev_priv)  in i965_irq_reset()  argument
4205 	struct intel_uncore *uncore = &dev_priv->uncore;  in i965_irq_reset()
4207 	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);  in i965_irq_reset()
4208 …intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT…  in i965_irq_reset()
4210 	i9xx_pipestat_irq_reset(dev_priv);  in i965_irq_reset()
4213 	dev_priv->irq_mask = ~0u;  in i965_irq_reset()
4216 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)  in i965_irq_postinstall()  argument
4218 	struct intel_uncore *uncore = &dev_priv->uncore;  in i965_irq_postinstall()
4226 	if (IS_G4X(dev_priv)) {  in i965_irq_postinstall()
4235 	intel_uncore_write(&dev_priv->uncore, EMR, error_mask);  in i965_irq_postinstall()
4238 	dev_priv->irq_mask =  in i965_irq_postinstall()
4253 	if (IS_G4X(dev_priv))  in i965_irq_postinstall()
4256 	GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);  in i965_irq_postinstall()
4260 	spin_lock_irq(&dev_priv->irq_lock);  in i965_irq_postinstall()
4261 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);  in i965_irq_postinstall()
4262 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i965_irq_postinstall()
4263 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);  in i965_irq_postinstall()
4264 	spin_unlock_irq(&dev_priv->irq_lock);  in i965_irq_postinstall()
4266 	i915_enable_asle_pipestat(dev_priv);  in i965_irq_postinstall()
4269 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)  in i915_hpd_irq_setup()  argument
4273 	lockdep_assert_held(&dev_priv->irq_lock);  in i915_hpd_irq_setup()
4277 	hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);  in i915_hpd_irq_setup()
4282 	if (IS_G4X(dev_priv))  in i915_hpd_irq_setup()
4287 	i915_hotplug_interrupt_update_locked(dev_priv,  in i915_hpd_irq_setup()
4296 	struct drm_i915_private *dev_priv = arg;  in i965_irq_handler()  local
4299 	if (!intel_irqs_enabled(dev_priv))  in i965_irq_handler()
4303 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i965_irq_handler()
4311 		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);  in i965_irq_handler()
4318 			hotplug_status = i9xx_hpd_irq_ack(dev_priv);  in i965_irq_handler()
4322 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in i965_irq_handler()
4325 			i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);  in i965_irq_handler()
4327 		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);  in i965_irq_handler()
4330 			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],  in i965_irq_handler()
4334 			intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],  in i965_irq_handler()
4338 			i9xx_error_irq_handler(dev_priv, eir, eir_stuck);  in i965_irq_handler()
4341 			i9xx_hpd_irq_handler(dev_priv, hotplug_status);  in i965_irq_handler()
4343 		i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);  in i965_irq_handler()
4346 	pmu_irq_stats(dev_priv, IRQ_HANDLED);  in i965_irq_handler()
4348 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);  in i965_irq_handler()
4384 void intel_irq_init(struct drm_i915_private *dev_priv)  in intel_irq_init()  argument
4386 	struct drm_device *dev = &dev_priv->drm;  in intel_irq_init()
4389 	INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);  in intel_irq_init()
4391 		dev_priv->l3_parity.remap_info[i] = NULL;  in intel_irq_init()
4394 	if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11)  in intel_irq_init()
4395 		to_gt(dev_priv)->pm_guc_events = GUC_INTR_GUC2HOST << 16;  in intel_irq_init()
4397 	if (!HAS_DISPLAY(dev_priv))  in intel_irq_init()
4400 	intel_hpd_init_pins(dev_priv);  in intel_irq_init()
4402 	intel_hpd_init_work(dev_priv);  in intel_irq_init()
4412 	dev_priv->display_irqs_enabled = true;  in intel_irq_init()
4413 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_irq_init()
4414 		dev_priv->display_irqs_enabled = false;  in intel_irq_init()
4416 	dev_priv->display.hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;  in intel_irq_init()
4423 	dev_priv->display.hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);  in intel_irq_init()
4425 	if (HAS_GMCH(dev_priv)) {  in intel_irq_init()
4426 		if (I915_HAS_HOTPLUG(dev_priv))  in intel_irq_init()
4427 			dev_priv->display.funcs.hotplug = &i915_hpd_funcs;  in intel_irq_init()
4429 		if (HAS_PCH_DG2(dev_priv))  in intel_irq_init()
4430 			dev_priv->display.funcs.hotplug = &icp_hpd_funcs;  in intel_irq_init()
4431 		else if (HAS_PCH_DG1(dev_priv))  in intel_irq_init()
4432 			dev_priv->display.funcs.hotplug = &dg1_hpd_funcs;  in intel_irq_init()
4433 		else if (DISPLAY_VER(dev_priv) >= 11)  in intel_irq_init()
4434 			dev_priv->display.funcs.hotplug = &gen11_hpd_funcs;  in intel_irq_init()
4435 		else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))  in intel_irq_init()
4436 			dev_priv->display.funcs.hotplug = &bxt_hpd_funcs;  in intel_irq_init()
4437 		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in intel_irq_init()
4438 			dev_priv->display.funcs.hotplug = &icp_hpd_funcs;  in intel_irq_init()
4439 		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)  in intel_irq_init()
4440 			dev_priv->display.funcs.hotplug = &spt_hpd_funcs;  in intel_irq_init()
4442 			dev_priv->display.funcs.hotplug = &ilk_hpd_funcs;  in intel_irq_init()
4460 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)  in intel_irq_handler()  argument
4462 	if (HAS_GMCH(dev_priv)) {  in intel_irq_handler()
4463 		if (IS_CHERRYVIEW(dev_priv))  in intel_irq_handler()
4465 		else if (IS_VALLEYVIEW(dev_priv))  in intel_irq_handler()
4467 		else if (GRAPHICS_VER(dev_priv) == 4)  in intel_irq_handler()
4469 		else if (GRAPHICS_VER(dev_priv) == 3)  in intel_irq_handler()
4474 		if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))  in intel_irq_handler()
4476 		else if (GRAPHICS_VER(dev_priv) >= 11)  in intel_irq_handler()
4478 		else if (GRAPHICS_VER(dev_priv) >= 8)  in intel_irq_handler()
4485 static void intel_irq_reset(struct drm_i915_private *dev_priv)  in intel_irq_reset()  argument
4487 	if (HAS_GMCH(dev_priv)) {  in intel_irq_reset()
4488 		if (IS_CHERRYVIEW(dev_priv))  in intel_irq_reset()
4489 			cherryview_irq_reset(dev_priv);  in intel_irq_reset()
4490 		else if (IS_VALLEYVIEW(dev_priv))  in intel_irq_reset()
4491 			valleyview_irq_reset(dev_priv);  in intel_irq_reset()
4492 		else if (GRAPHICS_VER(dev_priv) == 4)  in intel_irq_reset()
4493 			i965_irq_reset(dev_priv);  in intel_irq_reset()
4494 		else if (GRAPHICS_VER(dev_priv) == 3)  in intel_irq_reset()
4495 			i915_irq_reset(dev_priv);  in intel_irq_reset()
4497 			i8xx_irq_reset(dev_priv);  in intel_irq_reset()
4499 		if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))  in intel_irq_reset()
4500 			dg1_irq_reset(dev_priv);  in intel_irq_reset()
4501 		else if (GRAPHICS_VER(dev_priv) >= 11)  in intel_irq_reset()
4502 			gen11_irq_reset(dev_priv);  in intel_irq_reset()
4503 		else if (GRAPHICS_VER(dev_priv) >= 8)  in intel_irq_reset()
4504 			gen8_irq_reset(dev_priv);  in intel_irq_reset()
4506 			ilk_irq_reset(dev_priv);  in intel_irq_reset()
4510 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)  in intel_irq_postinstall()  argument
4512 	if (HAS_GMCH(dev_priv)) {  in intel_irq_postinstall()
4513 		if (IS_CHERRYVIEW(dev_priv))  in intel_irq_postinstall()
4514 			cherryview_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4515 		else if (IS_VALLEYVIEW(dev_priv))  in intel_irq_postinstall()
4516 			valleyview_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4517 		else if (GRAPHICS_VER(dev_priv) == 4)  in intel_irq_postinstall()
4518 			i965_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4519 		else if (GRAPHICS_VER(dev_priv) == 3)  in intel_irq_postinstall()
4520 			i915_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4522 			i8xx_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4524 		if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))  in intel_irq_postinstall()
4525 			dg1_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4526 		else if (GRAPHICS_VER(dev_priv) >= 11)  in intel_irq_postinstall()
4527 			gen11_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4528 		else if (GRAPHICS_VER(dev_priv) >= 8)  in intel_irq_postinstall()
4529 			gen8_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4531 			ilk_irq_postinstall(dev_priv);  in intel_irq_postinstall()
4546 int intel_irq_install(struct drm_i915_private *dev_priv)  in intel_irq_install()  argument
4548 	int irq = to_pci_dev(dev_priv->drm.dev)->irq;  in intel_irq_install()
4556 	dev_priv->runtime_pm.irqs_enabled = true;  in intel_irq_install()
4558 	dev_priv->irq_enabled = true;  in intel_irq_install()
4560 	intel_irq_reset(dev_priv);  in intel_irq_install()
4562 	ret = request_irq(irq, intel_irq_handler(dev_priv),  in intel_irq_install()
4563 			  IRQF_SHARED, DRIVER_NAME, dev_priv);  in intel_irq_install()
4565 		dev_priv->irq_enabled = false;  in intel_irq_install()
4569 	intel_irq_postinstall(dev_priv);  in intel_irq_install()
4581 void intel_irq_uninstall(struct drm_i915_private *dev_priv)  in intel_irq_uninstall()  argument
4583 	int irq = to_pci_dev(dev_priv->drm.dev)->irq;  in intel_irq_uninstall()
4591 	if (!dev_priv->irq_enabled)  in intel_irq_uninstall()
4594 	dev_priv->irq_enabled = false;  in intel_irq_uninstall()
4596 	intel_irq_reset(dev_priv);  in intel_irq_uninstall()
4598 	free_irq(irq, dev_priv);  in intel_irq_uninstall()
4600 	intel_hpd_cancel_work(dev_priv);  in intel_irq_uninstall()
4601 	dev_priv->runtime_pm.irqs_enabled = false;  in intel_irq_uninstall()
4611 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)  in intel_runtime_pm_disable_interrupts()  argument
4613 	intel_irq_reset(dev_priv);  in intel_runtime_pm_disable_interrupts()
4614 	dev_priv->runtime_pm.irqs_enabled = false;  in intel_runtime_pm_disable_interrupts()
4615 	intel_synchronize_irq(dev_priv);  in intel_runtime_pm_disable_interrupts()
4625 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)  in intel_runtime_pm_enable_interrupts()  argument
4627 	dev_priv->runtime_pm.irqs_enabled = true;  in intel_runtime_pm_enable_interrupts()
4628 	intel_irq_reset(dev_priv);  in intel_runtime_pm_enable_interrupts()
4629 	intel_irq_postinstall(dev_priv);  in intel_runtime_pm_enable_interrupts()
4632 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)  in intel_irqs_enabled()  argument
4634 	return dev_priv->runtime_pm.irqs_enabled;  in intel_irqs_enabled()